A novel wafer level bonding/debonding technique using an anti-adhesion layer for polymer-based zero-level packaging of RF device

2010 ◽  
Author(s):  
J. G. Kim ◽  
S. Seok ◽  
N. Rolland ◽  
P. A. Rolland
Keyword(s):  
Wafer Level ◽  
Adhesion Layer ◽  
Zero Level

Void formation and bond strength investigated for wafer-level Cu-Sn solid-liquid interdiffusion (SLID) bonding

2013 ◽  
Vol 2013 (1) ◽  
pp. 000717-000722
Author(s):  
Astrid-Sofie B. Vardøy ◽  
H.J. van de Wiel ◽  
Stian Martinsen ◽  
Greg R. Hayes ◽  
Hartmut R. Fischer ◽  
...  
Keyword(s):  
Shear Strength ◽  
Process Parameters ◽  
Storage Time ◽  
Void Formation ◽  
Wafer Level ◽  
Adhesion Layer ◽  
Lower Range ◽  
Thermal Budget ◽  
Application Analysis ◽  
Solid Liquid

A hermetic wafer-level Cu-Sn solid-liquid interdiffusion (SLID) bonding was investigated to explore the sensitivity of selected process parameters with regard to voiding and possible reduction of strength. Little or no variation was observed in the void density as a result of modifying the plated Sn-thickness, the storage time between plating and bonding, the bonding tool pressure, or the thermal budget during bonding. All shear tested samples showed excellent shear strength, with an average of 110 - 164 MPa. Some statistically significant differences in shear strength were found between the varied process parameters. However, the differences were too small to be critical for the application. Analysis of fracture surfaces showed that shear strengths in the lower range corresponded to fracture between the adhesion layer (TiW) and the silicon cap, while shear strengths in the higher range corresponded to fracture in the Cu3Sn formed during the bonding. The results indicate that the bonding process is robust with regard to the studied process parameters.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

Silicon Migration Seal Wafer-Level Vacuum Encapsulation

2020 ◽  
Vol 140 (7) ◽  
pp. 165-169
Author(s):  
Yukio Suzuki ◽  
Dupuit Victor ◽  
Toshiya Kojima ◽  
Yoshiaki Kanamori ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level

Development of Wafer Level Chip Size Packaging Process and its Application to the CMOS Image Sensor Module for Medical Device

2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  
Keyword(s):  
Medical Device ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Wafer Level ◽  
Packaging Process ◽  
Sensor Module ◽  
Chip Size

Low Temperature Al-Al Thermo-compression Bonding with Sn Oxidation Protect Layer for Wafer-level Hermetic Sealing

2016 ◽  
Vol 136 (6) ◽  
pp. 237-243 ◽  
Author(s):  
Shiro Satoh ◽  
Hideyuki Fukushi ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Low Temperature ◽  
Wafer Level ◽  
Hermetic Sealing

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

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