Application of Shadow Moir~ Technique to Board Level Manufacturing Technologies

Abstract During the search for the root cause of a board level failure, all aspects of the product must be revisited and investigated. These aspects encompass design, materials, and workmanship. In this discussion, the failure investigation involved an S-Band Power Amplifier assembly exhibiting abnormally low RF output power where initial troubleshooting did not provide a clear cause of failure. A detailed fault tree drove investigations that narrowed the focus to a few possible root causes. However, as the investigation progressed, multiple contributors were eventually discovered, some that were not initially considered.

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In-Situ Mechanical Sample Preparation of Selected Sites and Components on Large Modules and Boards

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0362 ◽

2016 ◽

Author(s):

Jim Colvin ◽

Timothy Hazeldine ◽

Heenal Patel

Keyword(s):

Sample Preparation ◽

Printed Circuit Board ◽

Circuit Board ◽

Tilt Table ◽

Standard Requirement ◽

Open Design ◽

Bga Packages ◽

Silicon Thickness ◽

Board Level

Abstract The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

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3D Integrated Power—A Discrete Perspective

ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2015p0141 ◽

2015 ◽

Author(s):

Ian Kearney ◽

Stephen Brink

Keyword(s):

Heat Dissipation ◽

Automatic Test Equipment ◽

Systematic Analysis ◽

Power Mosfet ◽

Root Cause ◽

Industry Standard ◽

Bona Fide ◽

Process Issue ◽

Board Level ◽

3D Package

Abstract The shift in power conversion and power management applications to thick copper clip technologies and thinner silicon dies enable high-current connections (overcoming limitations of common wire bond) and enhance the heat dissipation properties of System-in-Package solutions. Powerstage innovation integrates enhanced gate drivers with two MOSFETs combining vertical current flow with a lateral power MOSFET. It provides a low on-resistance and requires an extremely low gate charge with industry-standard package outlines - a combination not previously possible with existing silicon platforms. These advancements in both silicon and 3D Multi-Chip- Module packaging complexity present multifaceted challenges to the failure analyst. The various height levels and assembly interfaces can be difficult to deprocess while maintaining all the critical evidence. Further complicating failure isolation within the system is the integration of multiple chips, which can lead to false positives. Most importantly, the discrete MOSFET all too often gets overlooked as just a simple threeterminal device leading to incorrect deductions in determining true root cause. This paper presents the discrete power MOSFET perspective amidst the competing forces of the system-to-board-level failure analysis. It underlines the requirement for diligent analysis at every step and the importance as an analyst to contest the conflicting assumptions of challenging customers. Automatic Test Equipment (ATE) data-logs reported elevated power MOSFET leakage. Initial assumptions believed a MOSFET silicon process issue existed. Through methodical anamnesis and systematic analysis, the true failure was correctly isolated and the power MOSFET vindicated. The authors emphasize the importance of investigating all available evidence, from a macro to micro 3D package perspective, to achieve the bona fide path forward and true root cause.

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