Ceramic/Metal Composite Circuit-Board Level Technology for Application Specific Electronic Modules (ASEMs).

Abstract The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

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Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

Journal of Electronic Packaging ◽

10.1115/1.4007812 ◽

2012 ◽

Vol 134 (4) ◽

Cited By ~ 5

Author(s):

D. N. Borza ◽

I. T. Nistea

Keyword(s):

Solder Joint ◽

Fundamental Frequency ◽

Printed Circuit Board ◽

Speckle Interferometry ◽

Circuit Board ◽

Joint Failure ◽

Printed Circuit ◽

Out Of Plane ◽

Fringe Patterns ◽

Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.

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Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.423.26 ◽

2011 ◽

Vol 423 ◽

pp. 26-30

Author(s):

S. Assif ◽

M. Agouzoul ◽

A. El Hami ◽

O. Bendaou ◽

Y. Gbati

Keyword(s):

Solder Joint ◽

Printed Circuit Board ◽

Drop Test ◽

Dynamic Responses ◽

Circuit Board ◽

Joint Stress ◽

Printed Circuit ◽

Increasing Demand ◽

Improved Model ◽

Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

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Fabrication and integration of micro/nano-scale optical waveguides and photonic devices for application-specific planar optical integrated circuit board

10.1117/12.650119 ◽

2006 ◽

Author(s):

El-Hang Lee ◽

S. G. Lee ◽

B. H. O ◽

S. G. Park ◽

K. H. Kim

Keyword(s):

Integrated Circuit ◽

Optical Waveguides ◽

Photonic Devices ◽

Circuit Board ◽

Nano Scale ◽

Application Specific ◽

Optical Integrated Circuit

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Review of Printed-Circuit-Board Level EMI/EMC Issues and Tools

IEEE Transactions on Electromagnetic Compatibility ◽

10.1109/temc.2010.2044182 ◽

2010 ◽

Vol 52 (2) ◽

pp. 455-461 ◽

Cited By ~ 47

Author(s):

Bruce Archambeault ◽

Colin Brench ◽

Sam Connor

Keyword(s):

Printed Circuit Board ◽

Circuit Board ◽

Printed Circuit ◽

Board Level

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Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

Journal of Electronic Packaging ◽

10.1115/1.4005956 ◽

2012 ◽

Vol 134 (1) ◽

Cited By ~ 2

Author(s):

Hung-Jen Chang ◽

Chau-Jie Zhan ◽

Tao-Chih Chang ◽

Jung-Hua Chou

Keyword(s):

Printed Circuit Board ◽

Drop Test ◽

Circuit Board ◽

Printed Circuit Board Assembly ◽

Printed Circuit ◽

Plastic Ball ◽

Circuit Board Assembly ◽

Halogen Free ◽

Board Level ◽

The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

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