Simulation and Measurement of High Speed Serial Link Performance in a Dense, Thin Core Flip Chip Package

2006 ◽  
Author(s):  
M.J. Rowlands ◽  
S.G. Rosser
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Serial Link ◽  
Link Performance

SerDes Design and Modeling over 25+ Gb/s Serial Link

2011 ◽  
Vol 2011 (1) ◽  
pp. 000044-000060
Author(s):  
Pervez M. Aziz ◽  
Adam Healey ◽  
Cathy Liu ◽  
Freeman Zhong ◽  
Alex Zabroda
Keyword(s):  
High Speed ◽  
Forward Error Correction ◽  
Circuit Simulation ◽  
Signal Integrity ◽  
Systems Modeling ◽  
Behavioral Models ◽  
Noisy Environments ◽  
Serial Link ◽  
Link Performance ◽  
Forward Error

In this paper, signal integrity challenges for high speed serial link at 25 Gb/s, such as lossy channels and noisy environments are discussed. A few solution spaces to address those challenges are investigated, such as advanced equalization schemes, alternative signaling formats and forward error correction. It demonstrates that advanced signal processing enables long reach and extra long reach serial link performance at 25 Gb/s in next generation systems. Modeling methodologies used in SerDes behavioral models to ensure good correlation with transistor level circuit simulation are also discussed.

High-speed flip-chip InP/InGaAs avalanche photodiodes with ultralow capacitance and large gain-bandwidth products

1991 ◽  
Vol 3 (12) ◽  
pp. 1115-1116 ◽  
Author(s):  
Y. Kito ◽  
H. Kuwatsuka ◽  
T. Kumai ◽  
M. Makiuchi ◽  
T. Uchida ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Avalanche Photodiodes ◽  
Gain Bandwidth ◽  
Large Gain

Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
Short Circuit ◽  
Lead Free Solder ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Different Shapes ◽  
Free Solder ◽  
High Density Packaging

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

High Productivity Thermo-Compression Flip Chip Bonding

2014 ◽  
Vol 2014 (1) ◽  
pp. 000100-000106
Author(s):  
Tom Colosimo ◽  
Horst Clauberg ◽  
Evan Galipeau ◽  
Matthew B. Wasserman ◽  
Michael Schmidt-Lange ◽  
...  
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Flip Chip ◽  
Solder Joints ◽  
Rapid Heating ◽  
Temperature Cycle ◽  
Temperature Uniformity ◽  
Heating Rates ◽  
Heating And Cooling ◽  
Chip Technology

Advancements in electronic packaging performance and cost have historically been driven by higher integration primarily provided by fab shrinks that has followed the well-known Moore's law. However, due to the tremendous and continuously increasing cost of building new fabs, the performance/cost improvements achieved via node shrinks are negated. This leaves packaging innovation as the vehicle to achieve future cost-performance improvements. This has initiated a More-than-Moore idea that has led to vigorous R&D in packaging. Advanced packages which employ ultra-fine pitch flip chip technology for chip-to-substrate, chip-to-chip, or chip-to-interposer for the first level interconnect have been developed as an answer to obtaining higher performance. However, the costs are too high as compared to traditional wire bonding. The status today is that the fundamental technical hurdles of manufacturing the new advanced packages have been solved, but cost reduction and yield improvements have to be addressed for large-scale adoption into high volume manufacturing. In traditional flip chip assembly silicon chips are tacked onto a substrate and then the solder joints are melted and mass reflowed in an oven. This mass reflow technique is troublesome as the pitch of the solder bumps become finer. This is due to the large differences in the thermal expansion coefficient of the die and the substrate, which creates stress at the solder joints and warpage of the package when the die and substrate are heated and cooled together. To mitigate and resolve this issue, thermo-compression bonders have been developed which locally reflow the solder without subjecting the entire substrate to the heating and cooling cycle. This requires that the bondhead undergo heating past the melting point of solder and then cooling down to a low enough temperature to pick the next die from the wafer that is mounted to tape. Machines in the market today can accomplish this temperature cycle in 7 to 15 seconds. This is substantially slower than the standard flip chip process which leads to high cost and is delaying the introduction of these new packages. This paper shows a flip chip bonder with a new heating and cooling concept that will radically improve the productivity of thermo-compression bonding. Data and productivity cycles from this new bond head with heating rates of over 200°C/sec and cooling of faster than 100°C/sec are revealed. Experimental results are shown of exceptional temperature accuracy across the die of 5°C throughout the cycle and better than 3°C at the final heating stage. The high speed thermo-compression bonds are analyzed and the efficacy of the new concept is proven. Excellent temperature uniformity while heating rapidly is an absolute necessity for enabling good solder joints in a fast process. Without good temperature uniformity, additional dwell times need to be incorporated to allow heat to flow to all of the joints, negating any benefits from rapid heating. Whereas the current state-of-that-art is often to program temperature in steps, this bonder can be commanded and accurately follows more complex temperature profiles with great accuracy. Examples of how this profiling can be used to enhance the uniformity and integrity of the joints with non-conductive pastes, film, and without underfill along with the associated productivity improvements will be shown. Tests that show portability across platforms that will lead to set up time and yield improvements and are identified and quantified. Additionally new ideas for materials and equipment development to further enhance productivity and yield are explored.

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