Drop test reliability of wafer level chip scale packages

2005 ◽  
Author(s):  
M. Alajoki ◽  
Luu Nguyen ◽  
Jorma Kivilahti
Keyword(s):  
Drop Test ◽  
Test Reliability ◽  
Wafer Level

Larger Array Fine Pitch Wafer Level Package Drop Test Reliability

2009 ◽  
Author(s):  
Tiao Zhou ◽  
Robert Derk ◽  
Kaysar Rahim ◽  
Xuejun Fan
Keyword(s):  
Finite Element ◽  
Failure Mechanism ◽  
Solder Alloy ◽  
Test Data ◽  
Test Performance ◽  
Drop Test ◽  
Test Reliability ◽  
Array Size ◽  
Wafer Level ◽  
Test Experiment

In this study, drop test reliabilities of wafer level packages (WLP) are investigated. Failure mechanism, crack map and crack initiation location are presented. Failure rates of six groups defined by JEDEC are examined through both drop test experiment and finite element (FE) analysis with ANSYS software. Effects of component placement, PCB design, WLP structures, array size, pitch, and solder alloy are studied through drop test experiment per JESD22-B111 and finite element modeling. It is found that the primary failure mechanism of WLP drop test failures is fracture of intermetallic compound (IMC) at WLP side. During the drop test, solder joints at outer columns experience most stress and will fracture first. And the corner balls always fail first. The crack initiates at inner side of solder joint and propagates to the opposite side. When JEDEC recommended PCB is used for WLP drop test, the corner components fail first. This is different from the findings from BGA packages. It is confirmed that the dominant failure rate of corner WLP components is mainly due to the effect of mounting screws, rather than the intrinsic drop test reliability of WLP. Therefore, it is not appropriate to judge the drop test reliability of WLP with the drop test data for the corner components. Instead, middle component drop test data represent intrinsic shock resistance of WLP, and they should be used to represent the drop test performance of WLP. Drop test DOE results showed that WLP structure and material make visible difference. Non-soldermask defined (NSMD) PCB pad designs result in better drop reliability than SMD pads. With a given ball array, WLP with smaller pitch has worse drop reliability. As array size increases from 6×6 to 10×10 and 12×12, the drop test performance drops significantly. In addition, choice of solder alloy makes visible difference for WLP.

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

2011 ◽  
Author(s):  
Pushkraj Tumne ◽  
Vikram Venkatadri ◽  
Santosh Kudtarkar ◽  
Michael Delaus ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Bulk Solder ◽  
Consumer Electronics ◽  
Drop Test ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Failure Analysis of the Solder Joints in Flip-Chip BGA Packages under Free-Drop Test

2014 ◽  
Vol 936 ◽  
pp. 628-632 ◽  
Author(s):  
Guo Zheng Yuan ◽  
Xia Chen ◽  
Xue Feng Shu
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Ball Grid Array ◽  
Test Method ◽  
Drop Test ◽  
Test Reliability ◽  
Internal Crack ◽  
The Real ◽  
Plastic Ball ◽  
Free Drop

The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop condition meets the JEDEC22-B111 standards (pulse peak 1500g, pulse duration 0.5 ms) when dropping from the 650mm height . In the testing, according to the real-time changes of dynamic voltage, the relationship between drop times and different phases of package failure was analyzed. With the dye-penetrated method and optical microscopy, it was easy to observe the internal crack and failure locations. The growth mechanism of the cracks in solder joints under the condition of drop-free was analyzed and discussed.

Board level drop test reliability of IC packages

2005 ◽  
Author(s):  
T.C. Chai ◽  
S. Quek ◽  
W.Y. Hnin ◽  
E.H. Wong ◽  
J. Chia ◽  
...  
Keyword(s):  
Drop Test ◽  
Test Reliability ◽  
Board Level

scholarly journals Re-Test Reliability of Gustatory Testing and Introduction of the Sensitive Taste-Drop-Test

2018 ◽  
Vol 43 (5) ◽  
pp. 341-346 ◽  
Author(s):  
Alexander Fjaeldstad ◽  
Andreas Steenholt Niklassen ◽  
Henrique M Fernandes
Keyword(s):  
Drop Test ◽  
Test Reliability

2nd Level Reliability Improvement on WLCSP

2010 ◽  
Vol 2010 (1) ◽  
pp. 000333-000338
Author(s):  
Seungwook Park ◽  
Jupyo Hong ◽  
Changbae Lee ◽  
Sunhee Moon ◽  
Jinsoo Kim ◽  
...  
Keyword(s):  
Solder Ball ◽  
Coefficient Of Thermal Expansion ◽  
Drop Test ◽  
Wafer Level ◽  
Molding Process ◽  
Property Variation ◽  
Chip Scale Package ◽  
Low Modulus ◽  
Market Needs ◽  
Reliability Issue

Recently the package market is demanding the smaller package size and the lower impedance electrical path with a short interconnection. The wafer level chip scale package is one of them, which has the solution of the market needs above. However, WLCSP technology is still not fully accepted on the large device size that is larger than 5mm × 5mm. It needs to overcome 2nd level reliability issue on both solder joint and drop reliability test. To improve 2nd level reliability, we need to apply the longer stand–off design such as Cu –post and double solder ball instead of single solder ball, and low modulus material on polymer layer under the solder pad for releasing thermal stress which result in the solder joints crack due to CTEs (Coefficient of Thermal Expansion) mismatch between organic PCB and WLCSP. In this paper, the double ball structure is introduced as one of them can provide the longer stand off. In addition of improving 2nd level reliability and drop test it may need to apply different solder ball component properties to increase Thermal cycling and drop test. The WLCSP structured a double solder ball showed a better 2nd level reliability result. This paper describes the molding process for double ball process and 2nd level reliability by solder property variation.

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