Gold embrittlement of solder joints in wafer level chip scale package on printed circuit board with Ni/Au surface finish

2004 ◽  
Author(s):  
Xingjia Huang ◽  
S.W.R. Lee ◽  
Ming Li ◽  
W.T. Chen
Keyword(s):  
Surface Finish ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Wafer Level ◽  
Printed Circuit ◽  
Chip Scale Package ◽  
Gold Embrittlement

Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board

2000 ◽  
Author(s):  
John H. Lau ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Shear Stress ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Shear Creep ◽  
Printed Circuit ◽  
Chip Scale Package ◽  
Free Solder

Abstract In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt%Sn-3.5wt%Ag and 100wt%In. The 62wt%Sn-36wt%Pb-2wt%Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP solder joint reliability are investigated.

scholarly journals Sporadic Early Life Solder Ball Detachment Effects on Subsequent Microstructure Evolution and Fatigue of Solder Joints in Wafer-Level Chip-Scale Packages

2020 ◽  
Vol 17 (1) ◽  
pp. 13-22
Author(s):  
Simon Schambeck ◽  
Matthias Hutter ◽  
Johannes Jaeschke ◽  
Andrea Deutinger ◽  
Martin Schneider-Ramelow
Keyword(s):  
Thermal Loading ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Automotive Electronics ◽  
Wafer Level ◽  
Aging Effects ◽  
Chip Scale Package ◽  
Solder Balls

Abstract The combination of continuous miniaturization of electronics and the demanding reliability requirements for industrial and automotive electronics is one big challenge for emerging packaging technology. One aspect is to increase the understanding of the damage under environmental loading. Therefore, the solder joints of a wafer-level chip-scale package assembled on a printed circuit board (PCB) have been analyzed after a temperature cycling test. In the case of the investigated package, a limited number of joints did not form a proper mechanical connection with the PCB copper pad. Although not intended in the first place, these circumstances cause a detachment of those joints within the first few thermal cycles. However, this constellation offers a unique opportunity to compare the solder joint microstructure after thermomechanical loading (connected joints) with pure thermal loading (detached joints) located directly next to each other. It is shown that microstructure aging effects can be directly linked to regions in the joint with increased loading. This is particularly the case for detached joints, which could almost retain their initial microstructure up to the effect of the high-temperature part of the thermal profile. By means of finite element simulation, it is further possible to quantify the increased loading on adjacent joints if isolated solder balls detach from the board. In one case presented, the lifetime of the corner joint was calculated to reduce up to 85% only.

Effects of Void, Crack, and PCB Thickness on the Solder Joint Reliability of Wafer-Level Chip-Scale Package (WLCSP) Assemblies

2002 ◽  
Author(s):  
John Lau ◽  
Yida Zou ◽  
Sergio Camerlo
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Temperature Cycling ◽  
Circuit Board ◽  
J Integral ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Printed Circuit ◽  
Joint Reliability ◽  
Chip Scale Package

The creep analyses of solder-bumped wafer-level chip-scale package (WLCSP) on printed circuit board (PCB) subjected to temperature cycling loading are presented. Emphasis is placed on the effects of PCB thickness on the solder joint reliability of the WLCSP assembly. Also, the effects of crack-length on the crack tip characteristics such as the J-integral in the WLCSP solder joint are studied by the fracture mechanics method. Finally, the effects of voids on the crack growth in the WLCSP solder joint are investigated.

Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board

2002 ◽  
Vol 124 (2) ◽  
pp. 69-76 ◽  
Author(s):  
John H. Lau ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Shear Stress ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Shear Creep ◽  
Printed Circuit ◽  
Chip Scale Package ◽  
Free Solder

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt percent Sn-3.5wt percent Ag and 100wt percent In. The 62wt percent Sn-36wt percent Pb-2wt percent Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP Solder joint reliability are investigated.

Sign in / Sign up

Export Citation Format

Share Document