RF circuit integration using high Q copper inductors on organic substrate and solder-bumped flip chip technology

2004 ◽  
Author(s):  
Guo-Wei Xiao ◽  
Xiao Huo ◽  
P.C.H. Chan
Keyword(s):  
Flip Chip ◽  
Organic Substrate ◽  
High Q ◽  
Chip Technology ◽  
Circuit Integration ◽  
Rf Circuit

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Development of Novel Filler Technology for No-Flow and Wafer Level Underfill Materials

2005 ◽  
Vol 127 (2) ◽  
pp. 77-85 ◽  
Author(s):  
Slawomir Rubinsztajn ◽  
Donald Buckley ◽  
John Campbell ◽  
David Esler ◽  
Eric Fiveland ◽  
...  
Keyword(s):  
Cost Reduction ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Organic Substrate ◽  
Operating Speed ◽  
Wafer Level ◽  
Package Design ◽  
Chip Technology ◽  
Package Size ◽  
Package Reliability

Flip chip technology is one of the fastest growing segments of electronic packaging with growth being driven by the demands such as cost reduction, increase of input/output density, package size reduction and higher operating speed requirements. Unfortunately, flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate, which leads to premature failures of the package. Package reliability can be improved by the application of an underfill. In this paper, we report the development of novel underfill materials utilizing nano-filler technology, which provides a previously unobtainable balance of low CTE and good solder joint formation.

Applying system modeling to define 2.5 - d and 3 - d packaging roadmaps

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001983-002007
Author(s):  
Dev Gupta
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
System Modeling ◽  
New Technology ◽  
Smart Phone ◽  
Cost Effective ◽  
High Volume ◽  
Organic Substrate ◽  
Chip Technology ◽  
D Modules

Though work on 3-d and later 2.5-d packaging has been going on now for over 5 years, we do not yet see large applications in areas other than traditional heterogeneous integration e,g. in camera modules. Adoption of 2.5-d Si interposer technology in 2010-11 to build FPGA modules on a commercial scale had generated much enthusiasm and expectation that floodgates will open for wide use of this technology e,g. in every Smart Phone but that has not yet materialized, giving rise to a shift in attention in Blogs and Conferences from purely digital applications e,g. processor - memory modules to more performance driven and cost insensitive applications e,g. heterogeneous modules for electro - optic I/O in servers etc. Roadmaps for emerging technologies like 3-d stacking or 2.5-d modules are developed taking process maturity into consideration but they must also anticipate major applications. Such applications using a new technology can succeed only if there are overwhelming advantages in performance and system cost that negate increases in module costs. When the author and his team developed electroplated solder bump flip chip technology and their high volume implementation at two of the leading IDMs over 2 decades ago, both performance ( electrical ) and cost modeling were used to short list applications most likely to succeed and limit process development only for those applications. Countless users & providers of flip chip technology since then have benefited from this original work on electroplated solder and pillar bumps as well as build up type organic substrate technologies. A similar theoretical approach is sorely needed in the development of 2.5-d and 3-d technologies to define the most cost - effective configurations and focus development work on only those. In this work we will discuss the Bandwidth and Power consumption ( two of the key drivers for die stacking ) of various 2.5-d and 3-d package configurations and based on simulation results compare them. Key takeaways : 3-d stacking of dice using TSVs may not necessarily produce improved performance compared to less complicated packaging. Expensive interposers with high interconnect density may not even be necessary for most volume applications. Most likely configurations for processor - memory 3-d modules to get good enough bandwidth at lowest cost.

Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy

1996 ◽  
Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Flip Chip ◽  
Ultrasonic Waves ◽  
Acoustic Microscopy ◽  
Acoustic Microscope ◽  
Chip Technology ◽  
Ball Joints ◽  
Non Destructive ◽  
Scanning Acoustic Microscope

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

scholarly journals Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Electron Mobility Transistors ◽  
Wire Bonding ◽  
High Electron ◽  
Parasitic Inductance ◽  
Switching Performance ◽  
Turn On ◽  
Electron Mobility Transistors ◽  
Chip Technology ◽  
Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

Monolithic Thin Film Red LED Active-matrix Micro-display by Flip-chip Technology

2021 ◽  
pp. 1-1
Author(s):  
Peian Li ◽  
Xu Zhang ◽  
Wing Cheung Chong ◽  
Kei May Lau
Keyword(s):  
Thin Film ◽  
Flip Chip ◽  
Active Matrix ◽  
Chip Technology ◽  
Red Led
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