A novel no-flow flux underfill material for advanced flip chip packaging

2003 ◽  
Author(s):  
A.Y. Xiao ◽  
Q.K. Tong ◽  
J. Shah ◽  
P. Morganelli
Keyword(s):  
Flip Chip ◽  
Flip Chip Packaging ◽  
Flow Flux ◽  
Underfill Material

Development of No Flow Underfills for Lead-Free Flip Chip Applications

2006 ◽  
Author(s):  
Kaustubh Nagarkar ◽  
Tan Zhang ◽  
David Esler ◽  
David Simon ◽  
Paul Gillespie ◽  
...  
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Stencil Printing ◽  
Significant Research ◽  
Flip Chip Packaging ◽  
Chip Carrier ◽  
Packaging Industry ◽  
The Impact ◽  
Semiconductor Packaging ◽  
Underfill Material

Flip chip packaging is one of the fastest growing segments in electronics packaging technology. The semiconductor packaging industry is continuing to migrate towards Pb-free electronics assembly. Therefore, the development of compatible materials for Pb-free flip chip packaging is critical to this transition [1]. Flip chip devices are commonly underfilled to compensate for the mismatch in the Coefficient of Thermal Expansion (CTE) between the die and the chip carrier. The No Flow Underfill (NFU) process is a type that can increase the throughput of the flip chip assembly process and reduce manufacturing costs. Significant research has been performed to develop NFUs for eutectic applications. However, further research is required for the development of NFUs that are compatible with the Pb-free solders and the high temperature reflow process associated with these solders. In this paper, the challenges associated with the development of 'filled' underfill formulations for assembly with the 95.5Sn/3.8Ag/0.7Cu bumped flip chip devices are discussed. The effects of process variables that affect voiding in the underfill layer have been presented. The impact on voiding due to stencil printing of the underfill has been discussed. The impact on assembly reliability due to the underfill material properties has also been reported.

The Characterization of Underfill-Passivation Interface Under Monotonic and Fatigue Loading and Its Application to Flip Chip Reliability Prediction

2005 ◽  
Author(s):  
Saketh Mahalingam ◽  
Sandeep Tonapi ◽  
Suresh K. Sitaraman
Keyword(s):  
Reasonable Agreement ◽  
Flip Chip ◽  
Fatigue Loading ◽  
Reliability Prediction ◽  
Paris Law ◽  
Joint Reliability ◽  
Electrical Interconnection ◽  
Flip Chip Packaging ◽  
Underfill Material

Flip chip packaging technology is an attractive technique to achieve mechanical and electrical interconnection between the silicon chip and the substrate. Solder joint reliability in flip chip on organic board (FCOB) is enhanced by underfill application. The failure of solder joints in a flip chip package is usually associated with underfill delamination, esp. from the chip passivation. In this work, the fracture toughness of this interface is characterized for a novel no-flow underfill material using an innovative residual stress induced decohesion (RSID) test. Numerical modeling of the chip passivation-underfill interface indicates that the delamination will not progress under monotonic loading. However, the progress of delamination occurs under repeated thermal cycling. An empirical Paris law for underfill delamination has been developed and has been applied to predict delamination in actual flip chip packages. A reasonable agreement between the two is shown.

Thermal characterization of an epoxy-based underfill material for flip chip packaging

2000 ◽  
Vol 357-358 ◽  
pp. 1-8 ◽  
Author(s):  
Yi He ◽  
Brian E Moreira ◽  
Alan Overson ◽  
Stacy H Nakamura ◽  
Christine Bider ◽  
...  
Keyword(s):  
Flip Chip ◽  
Thermal Characterization ◽  
Flip Chip Packaging ◽  
Underfill Material

Effect of Warpage of Flip Chip Packages Due to the Underfill Encapsulating Process on Interconnect Reliability

2009 ◽  
Vol 131 (3) ◽  
Author(s):  
Satoru Katsurayama ◽  
Hironori Tohmyoh
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Capillary Flow ◽  
Curing Process ◽  
Assembly Process ◽  
Test Circuit ◽  
Interconnect Reliability ◽  
Flip Chip Packaging ◽  
Underfill Material

In flip chip packages, it is common practice for interconnects to be encapsulated with a liquid underfill material. This paper describes the effects of different underfill processes, i.e., the conventional capillary-flow underfill and two no-flow underfill processes, on flip chip packaging. The warpage of the package was examined, and the value of this during three different underfill encapsulating processes was measured. In addition, the interconnect reliability of the bump bonds after thermal-cycling was evaluated using a test circuit. The warpage of the package before curing varied depending on the assembly process, but that after curing was almost the same for all the processes studied. It was found that the interconnect reliability is closely related to the differences in the warpage arising from the assembly process, and that the smaller change in warpage introduced by the curing process gave a higher interconnect reliability for the bump bonds. Based on these findings, lower curing temperatures are considered to be more effective for improving the mountability of the package and the interconnect reliability.

Wafer Level Underfill Processing

2000 ◽  
Author(s):  
Luu Nguyen ◽  
Christopher Quentin ◽  
Phuong Nguyen
Keyword(s):  
Flip Chip ◽  
Process Conditions ◽  
Wafer Level ◽  
New Paradigm ◽  
Assembly Method ◽  
Flip Chip Packaging ◽  
The Subject ◽  
The Individual ◽  
Level Process ◽  
Underfill Material

Abstract Underfill materials play a major role in the reliability of flip chip packages. These adhesives have been the subject of much research and development in the last few years, and much improvement in material performance has been obtained. However, the assembly method still remains unchanged, with the underfill being dispensed at the individual die level after flip chip reflow. Even with the arrival of “no-flow” underfills, assembly still requires depositing the underfill material onto the flip chip site prior to positioning the flip chip die. Processing underfill at the wafer level brings in a new paradigm shift to the area of flip chip packaging. Precoating the wafer with the underfill will create significant savings in both time and money. The application cycle time of the wafer level process becomes equivalent to a single dispensing operation for all the good dies on the wafer. This paper will present results obtained with screen printing used as the application method for the wafer level process. An experimental underfill was printed onto un-bumped silicon wafers and cured, and the resultant films were analyzed. Process conditions affecting film thickness and surface roughness were evaluated. Preliminary results with bumped wafers are also discussed.

A High-Linearity 76–85-GHz 16-Element 8-Transmit/8-Receive Phased-Array Chip With High Isolation and Flip-Chip Packaging

2014 ◽  
Vol 62 (10) ◽  
pp. 2337-2356 ◽  
Author(s):  
Bon-Hyun Ku ◽  
Ozgur Inac ◽  
Michael Chang ◽  
Hyun-Ho Yang ◽  
Gabriel M. Rebeiz
Keyword(s):  
Flip Chip ◽  
Phased Array ◽  
High Isolation ◽  
High Linearity ◽  
Flip Chip Packaging
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