Thermocompression bonding of aluminum bumps in TAB applications

2002 ◽  
Author(s):  
S.K. Kang
Keyword(s):  
Thermocompression Bonding

Thermocompression Bonding to GaP Crystals

1963 ◽  
Vol 2 (4) ◽  
pp. 251-252
Author(s):  
Tsunekatsu Fukui ◽  
Makoto Kikuchi
Keyword(s):  
Thermocompression Bonding

Flip-Chip Flux Evolution

2019 ◽  
Vol 2019 (1) ◽  
pp. 000115-000119 ◽  
Author(s):  
Andy Mackie ◽  
Hyoryoon Jo ◽  
Sze Pei Lim
Keyword(s):  
Flip Chip ◽  
Elevated Temperatures ◽  
High Volume ◽  
Automotive Electronics ◽  
Assembly Process ◽  
Surface Finishes ◽  
Solder Bumps ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
Flip Chip Assembly

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

Evaluation of Cu/Sn-Cu Bump Bonding Processes for 3D Integration Using a Fluxing Adhesive

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001726-001742
Author(s):  
Alan Huffman ◽  
Jason Reed ◽  
Matthew Lueck ◽  
Christopher Gregory ◽  
Dorota Temple ◽  
...  
Keyword(s):  
High Pressures ◽  
Bonding Process ◽  
Self Assembled Monolayers ◽  
Environmental Damage ◽  
3D Integration ◽  
Chemical Cleaning ◽  
Plasma Pretreatment ◽  
Assembled Monolayers ◽  
Thermocompression Bonding ◽  
Oxide Removal

The study of copper-based bump structures for interconnects in 3D integration applications has been ongoing for several years. Typically, an array of Cu bumps is bonded to an array of Sn-capped Cu bumps or another Cu bump array using a thermocompression bonding process. These processes rely on high pressures and temperatures to facilitate bonding between the bump arrays. In order for this bonding to take place, some method of oxide removal is normally required for the Cu and/or Cu/Sn bump surfaces before bonding. A number of different methods have been investigated by a number of groups, including chemical cleaning, plasma cleaning, self-assembled monolayers, and no-flow underfill (NUF) materials. The use of NUFs is particularly intriguing, since these materials can be formulated with fluxing agents which could reduce surface oxides on Cu and Sn and can be deposited immediately prior to the thermocompression bonding process. In addition, the material provides a protective encapsulant to the interconnect array, protecting it from environmental damage and adding mechanical strength to the assembly. We will present the results of a study to evaluate new fluxing NUF materials in thermocompression bonding processes on full area array test devices with 25 micron bump pitch. The test devices are fabricated with either Cu or Cu/Sn bumps to provide two different bonding options (Cu to Cu or Cu/Sn to Cu). We will compare the NUF bonding process and resulting bonded interfaces to assemblies fabricated using our standard bonding processes, which rely on both chemical and plasma pretreatment processes to prepare the bump arrays before bonding. Mechanical and electrical data will be used to compare the two bonding processes, as well as SEM cross-section analysis of the bonded interfaces.

Hybrid Bonding Methods Using Ultra Precision Cutting for 3D-SIC

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001701-001730
Author(s):  
Taiji Sakai ◽  
Nobuhiro Imaizumi ◽  
Masataka Mizukoshi ◽  
Masayuki Kawase ◽  
Ryoji Tanimoto ◽  
...  
Keyword(s):  
Narrow Gap ◽  
Oxidation Layer ◽  
Solid Diffusion ◽  
Fine Pitch ◽  
Single Crystal Diamond ◽  
Thermocompression Bonding ◽  
Ultra Precision ◽  
Lower Height ◽  
Cu Oxidation ◽  
Bonding Technique

We have developed Cu-Cu/adhesives hybrid bonding technique by using collective cutting of Cu bumps and adhesives in order to achieve high density 3D-SIC. It is considered that progression of fine pitch interconnection leads to lower height of bonding electrodes, resulting in narrow gap between 3D-SICs. Therefore, it is difficult to fill in adhesive to such a narrow gap 3D-SICs after bonding, so we consider that hybrid bonding of pre-applied adhesives and Cu-Cu thermocompression bonding must be advantageous, in terms of void less bonding and minimizing bonding stress by adhesives and also low electricity by Cu-Cu solid diffusion bonding. In the present study, we adapted the following process; at first adhesives were spin coated on the wafer with Cu post and then pre-baked. After that, pre-applied adhesives and Cu bumps were successfully cut by single crystal diamond bite. Typical adhesives may cause bite damage with continuous cutting, but in this research, we selected low damage adhesive against continuous cutting, which is important properties to commercial uses. Then, chips with adhesives were attached to substrates and Cu oxidation layer was removed by exposing formic acid atmosphere. Finally permanent bonding was done at 225 degree C for 30 minutes. We concluded that solid diffusion between bonded Cu bumps could be achieved and no adhesive residue could be seen between bonded interfaces by TEM/EDX analysis.

Multiphysics Modeling of Underfill Flow and Cure during Thermocompression Bonding

2015 ◽  
Vol 2015 (1) ◽  
pp. 000526-000529
Author(s):  
Mark Oliver ◽  
Nagi Elabbasi
Keyword(s):  
Dynamic Viscosity ◽  
Temperature Profiles ◽  
Process Variables ◽  
Degree Of Cure ◽  
Multiphysics Modeling ◽  
Conductive Film ◽  
Underfill Flow ◽  
Thermocompression Bonding

We present a model of fillet formation and cure during thermocompression bonding with a non-conductive film. Process variables in the model include the position and temperature profiles applied to the silicon die and substrate by the bonding tool. The chemorheology of the underfill is accounted for in order to track the degree of cure of the material and its impact on dynamic viscosity. Simulation predictions of how the underfill chemorheology impacts the fillet shape and level of cure advance during the processes are presented.

Assembly Equipment Requirements for Next Generation Advanced Packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000321-000325
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Tom Strothmann
Keyword(s):  
Capital Investment ◽  
Flip Chip ◽  
High Volume ◽  
Electrical Performance ◽  
Wafer Level ◽  
Considerable Uncertainty ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
The Impact ◽  
3D Package

Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.

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