Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance

2007 ◽  
Author(s):  
Alex Shye ◽  
Tipp Moseley ◽  
Vijay Janapa Reddi ◽  
Joseph Blomstedt ◽  
Daniel A. Connors
Keyword(s):  
Fault Tolerance ◽  
Transient Fault ◽  
Multiple Cores ◽  
Process Level

PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures

2009 ◽  
Vol 6 (2) ◽  
pp. 135-148 ◽  
Author(s):  
A. Shye ◽  
J. Blomstedt ◽  
T. Moseley ◽  
V.J. Reddi ◽  
D.A. Connors
Keyword(s):  
Fault Tolerance ◽  
Multicore Architectures ◽  
Transient Fault

Transient Fault Tolerance and System Safety Enhancement Based on System Theory

2011 ◽  
Vol 6 (10) ◽  
Author(s):  
Xiongfeng Huang ◽  
Chunjie Zhou ◽  
Yuanqing Qin ◽  
Ye Wang ◽  
Mingyue Yang
Keyword(s):  
System Theory ◽  
Fault Tolerance ◽  
System Safety ◽  
Transient Fault ◽  
Safety Enhancement

Survey on Fault Tolerance Startgies for Advance Microelectronics Chip

2019 ◽  
Vol 7 (1) ◽  
pp. 01-04
Author(s):  
Himanshu Shekhar, Prof. Deepa Gianchandani
Keyword(s):  
Fault Tolerance ◽  
Power Supply ◽  
Fault Tolerant ◽  
Full Adder ◽  
Equipment Design ◽  
Transient Faults ◽  
Transient Fault

In the complex advance microelectronics based system, handling units are managing gadgets of littler size, which are delicate to the transient faults. A framework should be fabricated that will perceive the presence of faults and fuses strategies to will endure these faults without troublesome the typical activity A transient fault happens in a circuit caused by the electromagnetic commotions, astronomical beams, crosstalk and power supply clamor. It is extremely hard to recognize these faults amid disconnected testing. Subsequently a region effective fault tolerant full adder for testing and fixing of transient and changeless faults happened in single and multi-net is proposed. Furthermore, the proposed design can likewise identify and fix perpetual faults. This structure acquires much lower equipment overheads with respect to the conventional equipment design. In this paper, talk about various fault tolerant methodology for CMOS and ICs.

Enhancing transient fault tolerance in embedded systems through an OS task level redundancy approach

2018 ◽  
Vol 87 ◽  
pp. 58-65 ◽  
Author(s):  
Seyyed Amir Asghari ◽  
Mohammadreza Binesh Marvasti ◽  
Amir M. Rahmani
Keyword(s):  
Fault Tolerance ◽  
Embedded Systems ◽  
Transient Fault ◽  
Task Level

Transient fault-tolerance through algorithms

2006 ◽  
Vol 25 (5) ◽  
pp. 25-30 ◽  
Author(s):  
G.K. Saha
Keyword(s):  
Fault Tolerance ◽  
Transient Fault

A dual process redundancy approach to transient fault tolerance for ccNUMA architecture

2013 ◽  
Vol 122 ◽  
pp. 50-57 ◽  
Author(s):  
Xingjun Zhang ◽  
Endong Wang ◽  
Feilong Tang ◽  
Meishun Yang ◽  
Hengyi Wei ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Dual Process ◽  
Transient Fault
Sign in / Sign up

Export Citation Format

Share Document