Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata

2018 ◽  
Author(s):  
Frank Sill Torres ◽  
Robert Wille ◽  
Marcel Walter ◽  
Philipp Niemann ◽  
Daniel GroBe ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata ◽  
The Impact

Accurate reliability analysis method for quantum-dot cellular automata circuits

2015 ◽  
Vol 29 (29) ◽  
pp. 1550203
Author(s):  
Huanqing Cui ◽  
Li Cai ◽  
Sen Wang ◽  
Xiaoqiang Liu ◽  
Xiaokuo Yang
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Fault Tree ◽  
The Novel ◽  
Binary Decision ◽  
Quantum Dot Cellular Automata ◽  
Input Signals ◽  
Tree Models ◽  
The Impact ◽  
Qca Circuits

Probabilistic transfer matrix (PTM) is a widely used model in the reliability research of circuits. However, PTM model cannot reflect the impact of input signals on reliability, so it does not completely conform to the mechanism of the novel field-coupled nanoelectronic device which is called quantum-dot cellular automata (QCA). It is difficult to get accurate results when PTM model is used to analyze the reliability of QCA circuits. To solve this problem, we present the fault tree models of QCA fundamental devices according to different input signals. After that, the binary decision diagram (BDD) is used to quantitatively investigate the reliability of two QCA XOR gates depending on the presented models. By employing the fault tree models, the impact of input signals on reliability can be identified clearly and the crucial components of a circuit can be found out precisely based on the importance values (IVs) of components. So this method is contributive to the construction of reliable QCA circuits.

Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale

2021 ◽  
pp. 1-1
Author(s):  
Alfonso Sanchez-Macian ◽  
Alonso Martin-Toledano ◽  
Jefferson Andres Bravo-Montes ◽  
Francisco Garcia-Herrero ◽  
Juan Antonio Maestro
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata ◽  
Nano Scale ◽  
The Impact

On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata

2020 ◽  
Vol 76 ◽  
pp. 103109 ◽  
Author(s):  
Frank Sill Torres ◽  
Pedro A. Silva ◽  
Geraldo Fontes ◽  
Marcel Walter ◽  
José Augusto M. Nacif ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata ◽  
The Impact

Improved Quantum Dot Cellular Automata 4:1 Multiplexer Circuit Unit

2014 ◽  
Vol 2014 (1) ◽  
pp. 37-44 ◽  
Author(s):  
Arighna Sarkar ◽  
◽  
Debarka Mukhopadhyay ◽  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

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