Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits

In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

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System-Level Leakage Power Estimation Model for ASIC Designs

Advances in Electrical and Electronic Engineering ◽

10.15598/aeee.v16i3.2947 ◽

2018 ◽

Vol 16 (3) ◽

Author(s):

Abhishek Narayan Tripathi ◽

Arvind Rajawat

Keyword(s):

Power Estimation ◽

Leakage Power ◽

System Level ◽

Estimation Model

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Leakage power estimation and minimization in configurable logic block of FPGA

2008 International Conference on Computer and Communication Engineering ◽

10.1109/iccce.2008.4580610 ◽

2008 ◽

Author(s):

A. K. Kureshi ◽

Mohd. Hasan

Keyword(s):

Power Estimation ◽

Leakage Power ◽

Logic Block

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Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Lecture Notes in Computer Science ◽

10.1007/978-3-642-24154-3_18 ◽

2011 ◽

pp. 173-179 ◽

Cited By ~ 1

Author(s):

Alireza Khosropour ◽

Hossein Aghababa ◽

Ali Afzali-Kusha ◽

Behjat Forouzandeh

Keyword(s):

Extreme Value Distribution ◽

Power Estimation ◽

Extreme Value ◽

Leakage Power ◽

Value Distribution ◽

Generalized Extreme Value Distribution ◽

Generalized Extreme Value

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Power Estimation and Power Noise Analysis for CMOS Circuits

Journal of Circuits System and Computers ◽

10.1142/s0218126697000036 ◽

1997 ◽

Vol 07 (01) ◽

pp. 17-30 ◽

Cited By ~ 1

Author(s):

An-Chang Deng

Keyword(s):

Power Consumption ◽

Power Supply ◽

Noise Analysis ◽

Power Estimation ◽

Primary Concern ◽

Cmos Circuits ◽

Input Stimulus ◽

Circuit Performance ◽

Supply Noise ◽

Power Noise

Power consumption is a primary concern for today's IC designers. However, determining an IC's power consumption is a difficult task, as consumption varies according to input stimulus conditions. This paper will focus on (1) the principal phenomena involved in the power consumption of CMOS circuits, (2) a brief survey of power estimation techniques, and (3) the effect of power-supply noise on circuit performance plus possible solutions to this problem.

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