Survey of Test Data Compression Technique Emphasizing Code Based Schemes

2009 ◽  
Author(s):  
Usha Sandeep Mehta ◽  
K.S. Dasgupta ◽  
N.M. Devashrayee
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Test Data Compression ◽  
Compression Technique

Test data compression technique based on partial data block reuse in SoC

2010 ◽  
Vol 24 (5) ◽  
pp. 487-493
Author(s):  
Yiming Ouyang ◽  
Xi'e Huang ◽  
Huaguo Liang ◽  
Baosheng Zou
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Data Block ◽  
Test Data Compression ◽  
Compression Technique ◽  
Partial Data

SoC Test Data Compression Technique Based on RLE-G

2010 ◽  
Vol 439-440 ◽  
pp. 1595-1600
Author(s):  
Chun Jian Deng ◽  
Liu Wei ◽  
Xi Feng Zheng ◽  
Liang Yang
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Test Time ◽  
Test Data Compression ◽  
Compression Technique ◽  
Current Test ◽  
Soc Test ◽  
Efficient Test ◽  
Data Volume ◽  
Test Vectors

Test data compression has been an effective way to reduce test data volume and test time, as well as to solve automatic test equipment (ATE) memory and bandwidth limitation. We analyze the limitations of current test data compression algorithm and draw on the previous experience to deduce an optimal compression coding model suitable for SoC test data. In addition, in this paper we make full use of the relevance of the test vectors and the advantages of statistical coding to present an efficient test data compression method RLE-G based on the coding model, and give the RLE-G the optimal compression efficiency of the boundary conditions and realization steps. The experimental results for ISCAS 89 benchmark circuits demonstrate RLE-G have the excellent advantages of high compression ratio.

scholarly journals Efficient Test Data Compression for SoC through ASRL with Improved Dictionary based Compression Technique

2019 ◽  
Vol 8 (11) ◽  
pp. 3591-3597
Keyword(s):  
Embedded System ◽  
Data Compression ◽  
Test Data ◽  
Compression Ratio ◽  
Test Data Compression ◽  
Bandwidth Utilization ◽  
Compression Technique ◽  
Memory Size ◽  
Efficient Test ◽  
Effective Manner

Data compression techniques are explored in this paper, through which system memory size gets reduced in an effective manner. The size of the memory is always a key constraint in the embedded system. Larger memory size increases the bandwidth utilization which raises the cost of hardware and data transmission. It is difficult to transfer large data through the network. Data compression encoding technique is utilized to minimize the data size. The redundant character is reduced or encoding the bits in data is done to reduce the data size. The proposed system focused on lossless compression where the original information of the data is available even though the data size is compressed. The data compression is done through a dictionary-based compression algorithm and Alternating Statistical Run Length code (ASRL). In the existing system of ASRL, the compression ratio is about 65.16% and 67.18% for two benchmark circuits S5378 &S9234. The compression ratio of the test data is increased by combining the ASRL and Improved Dictionary-Based compression Technique. The proposed combined technique provides 80.25%& 82.5% compression ratio for two benchmark circuits S5378 &S9234. This reduces the power dissipation problem in the circuit and thereby the area of the circuit gets reduced.

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