Tunnel FET-based pass-transistor logic for ultra-low-power applications

2011 ◽  
Author(s):  
Sung Hwan Kim ◽  
Zachery A. Jacobson ◽  
Pratik Patel ◽  
Chenming Hu ◽  
Tsu-Jae King Liu
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Tunnel Fet ◽  
Pass Transistor ◽  
Pass Transistor Logic

scholarly journals Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

2019 ◽  
Vol 9 (1) ◽  
pp. 4340-4347
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Digital Design ◽  
Total Power ◽  
Power Comparison ◽  
Ultra Low Power ◽  
Power Efficient ◽  
Area Efficiency ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper we propose a power efficient technique called Sleepy- Gate Diffusion Input (S-GDI) that can be used for efficient digital design at nano scale foundries. For area and power comparison, ten prior techniques are taken in to consideration and applied on XOR gate, 1-bit adder, 1-bit comparator and 4- bit up-down counter. All techniques are parametrically analyzed on 65nm technology. The proposed S-GDI technique has been observed power efficient as compared to Complementary CMOS technique (CCT), Complementary Pass Transistor Logic (CPTL), DCMOS (Differential CMOS), Differential Cascode Voltage Switch with Pass Gate Logic (DCVSPG), Energy Economized Pass Transistor Logic (EEPL), Lean Integration with Pass Transistors (LEAP), Push-Pull Pass Transistor Logic (PPL), Pass Transistor Logic (PTL), CMOS with Transmission Gate (TG) and Gate diffusion Input (GDI). As compared to GDI technique S-GDI is showing 96.20%, 93.65%, 97.88% and 98.22% power efficiency for XOR, 1-bit adder, 1-bit comparator and 4-bit up-down counter respectively. S-GDI is showing area efficiency of 17.16% and 28.1% for XOR, 41.26% and 53.89% for 1-bit adder, 7.6% and 21.76% for 1-bit comparator and 6.7% and 28% for up-down counter over EEPL and DCMOS technique respectively. Although other techniques except EEPL and DCMOS techniques are area efficient as compared to proposed technique but this is on the expense of higher total power dissipation. So, PDP (power delay products) of all considered techniques are also calculated on 65nm technology for both SUM and CARRY outputs of 1-bit adder. In both cases power delay product for S-GDI technique is very less as compared to all other considered technique. Due to efficiency of S-GDI in terms of considered parameters, this technique can be efficiently used for low power applications

Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications

2018 ◽  
Author(s):  
Libo Yang ◽  
Jiadi Zhu ◽  
Cheng Chen ◽  
Zhixuan Wang ◽  
Zexue Liu ◽  
...  
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Tunnel Fet

An Ultra-Low-Power Black Phosphorus (B-Ph)/Si Heterojunction Dopingless-Tunnel FET (HD-TFET) with Enhanced Electrical Characteristics

2021 ◽  
Vol 149 ◽  
pp. 106752
Author(s):  
Rahul Misra ◽  
Kunal Singh ◽  
Mirgender Kumar ◽  
Ravi Rastogi ◽  
Arun Kumar ◽  
...  
Keyword(s):  
Low Power ◽  
Black Phosphorus ◽  
Electrical Characteristics ◽  
Ultra Low Power ◽  
Tunnel Fet
Sign in / Sign up

Export Citation Format

Share Document