Chip-size and power consumption of ASICs and digital signal processors for low-power signal-processing

2002 ◽  
Author(s):  
W. Vollenweider
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Low Power ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Chip Size ◽  
Signal Processors

scholarly journals Approximate Adder Implementation using Quantum- Dot Cellular Automata for Digital Signal Processing

2019 ◽  
Vol 9 (2) ◽  
pp. 3743-3748
Keyword(s):  
Signal Processing ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Digital Signal ◽  
Error Resilience ◽  
Digital Signal Processors ◽  
Approximate Computing ◽  
Quantum Dot Cellular Automata ◽  
Area Efficiency ◽  
Signal Processors

We explore quantum-dot cellular automata (QCA) design for approximate computing units in digital signal processors. For this cause, a common approach for design is introduced, and approximation-oriented mirror adders (AMA) are developed. In this work, we compromise power/area efficiency of circuit-level design with accuracy supervision. We compare Approximate Mirror Adder cells designed using conventional CMOS technique and using QCA. Our technique picks fairly accurate adder designs that minimalize the over-all area, hitherto maintaining the ultimate performance by studying their error resilience.

Digital signal processors for a signal processing laboratory

1999 ◽  
Vol 42 (3) ◽  
pp. 192-199 ◽  
Author(s):  
L. Moreno ◽  
J.F. Sigut ◽  
J.J. Merino ◽  
J.I. Estevez ◽  
J.L. Sanchez ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Signal Processors

scholarly journals Design of High-Speed Low Power Computational Blocks for DSP Processors

2021 ◽  
Vol 11 (2) ◽  
pp. 1419-1429
Author(s):  
Alivelu Manga N.
Keyword(s):  
Signal Processing ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Large Scale ◽  
Power Optimization ◽  
Digital Signal ◽  
Oxide Semiconductor ◽  
Performance Criteria

In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

Introducing Undergraduate Students to The Use of Digital Signal Processors

1994 ◽  
Vol 31 (1) ◽  
pp. 66-83 ◽  
Author(s):  
N. Dahnoun ◽  
F. S. Schlindwein
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Undergraduate Students ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Signal Processing Algorithms ◽  
Processing Algorithms ◽  
Signal Processors

Introducing undergraduate students to the use of digital signal processors This article describes a procedure for teaching undergraduate students the implementation of digital signal processing algorithms (using the TMS320C25). Material used, description of the processor, examples and working assembly codes are presented.

scholarly journals Enhanced and Efficient Carry Select Adder with Minimal Delay

2021 ◽  
Author(s):  
G. Srividhya ◽  
T. Sivasakthi ◽  
R. Srivarshini ◽  
P. Varshaa ◽  
S. Vijayalakshmi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Signal Processors ◽  
Digital World ◽  
Carry Select Adder ◽  
Image Processors ◽  
Improved Model ◽  
Signal Processors

In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

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