IEEE 1149.1 based defect and fault tolerant scan chain for wafer scale integration

2004 ◽  
Author(s):  
Meng Lu ◽  
Yvon Savaria ◽  
Bing Qiu ◽  
J. Taillefer
Keyword(s):  
Fault Tolerant ◽  
Wafer Scale ◽  
Wafer Scale Integration ◽  
Ieee 1149.1 ◽  
Scan Chain ◽  
Scale Integration

Wafer scale integration

1988 ◽  
Vol 135 (6) ◽  
pp. 281
Author(s):  
J.B. Butcher ◽  
K.K. Johnstone
Keyword(s):  
Wafer Scale ◽  
Wafer Scale Integration ◽  
Scale Integration

AREA EFFICIENT LAYOUT OF BALANCED HYPERCUBES

1995 ◽  
Vol 06 (04) ◽  
pp. 631-645 ◽  
Author(s):  
KE HUANG ◽  
JIE WU
Keyword(s):  
Efficient System ◽  
Strong Connectivity ◽  
Wafer Scale ◽  
System Reconfiguration ◽  
Faulty Processor ◽  
Balanced Hypercube ◽  
Wafer Scale Integration ◽  
Scale Integration ◽  
Area Efficient ◽  
Load Balanced

As a multicomputer structure, the balanced hypercube is a variant of the standard hypercube for multicomputers, with desirable properties of strong connectivity, regularity, and symmetry. This structure is a special type of load balanced graph designed to tolerate processor failure. In balanced hypercubes, each processor has a backup (matching) processor that shares the same set of neighboring nodes. Therefore, tasks that run on a faulty processor can be reactivated in the backup processor to provide efficient system reconfiguration. In this paper, we study the implementation of balanced hypercubes in VLSI using the Wafer Scale Integration (VLSI/WSI) technology. Emphasis is on VLSI/WSI layout and area estimates. Our results show that the balanced hypercube can be implemented at least as efficient as the standard hypercube in an area layout and more efficient in a linear layout.

A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration

2019 ◽  
Vol 27 (2) ◽  
pp. 304-315
Author(s):  
Nicolas Laflamme-Mayer ◽  
Gilbert Kowarzyk ◽  
Yves Blaquiere ◽  
Yvon Savaria ◽  
Mohamad Sawan
Keyword(s):  
Wafer Scale ◽  
Wafer Scale Integration ◽  
Scale Integration
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