Reconfigurable architectures for mesh-arrays with PE and link faults

2002 ◽  
Author(s):  
I. Takanami ◽  
T. Horita
Keyword(s):  
Reconfigurable Architectures

High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures

2011 ◽  
Vol 30 (11) ◽  
pp. 1599-1609 ◽  
Author(s):  
Yongjoo Kim ◽  
Jongeun Lee ◽  
A. Shrivastava ◽  
J. W. Yoon ◽  
Doosan Cho ◽  
...  
Keyword(s):  
High Throughput ◽  
Coarse Grained ◽  
Reconfigurable Architectures ◽  
Data Mapping ◽  
High Throughput Data

Dagstuhl-Seminar “Dynamically and Partially Reconfigurable Architectures” (Dynamisch und partiell rekonfigurierbare Architekturen)

2004 ◽  
Vol 46 (4) ◽  
Author(s):  
Jürgen Becker
Keyword(s):  
Information Technology ◽  
Parallel Computing ◽  
Computer Science ◽  
Mobile Communication ◽  
Data Stream ◽  
Electrical Engineering ◽  
Reconfigurable Architectures ◽  
Automotive Application ◽  
Partial Reconfiguration ◽  
Computing Technique

SummaryThe paper addresses people from information technology, electrical engineering, computer science, and related areas. It gives an introduction and classification to fine-, coarse-, as well as multi-grain reconfigurable architectures. This data-stream-based and transport-triggered parallel computing technique in combination with dynamical and partial reconfiguration features demonstrates promising perspectives for future CMOS-based microelectronic solutions in multimedia and infotainment, mobile communication, as well as automotive application domains, among others.

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