Effect of gate length on the performance of InGaAs/InAs/InGaAs composite channel DMDG-HEMT devices

Author(s):  
R. Ranjani ◽  
R. Vaishnavi ◽  
N. Mohankumar ◽  
A. Mohanbabu
2007 ◽  
Vol 51 (6) ◽  
pp. 838-841 ◽  
Author(s):  
Dongmin Liu ◽  
Mantu Hudait ◽  
Yong Lin ◽  
Hyeongnam Kim ◽  
Steven A. Ringel ◽  
...  

2020 ◽  
Vol XVII (2) ◽  
pp. 23-33
Author(s):  
Faisal Hafeez ◽  
Salman Hussain ◽  
Wasim Ahmad ◽  
Mirza Jahanzaib

This paper presents the study to investigate the effects of binder ratio, in-gate length and pouring height on hardness, surface roughness and casting defects of sand casting process. Taguchi methodology with L9 orthogonal array was employed to design the experimentation. Sand casting of six blade impeller using A356 alloy was performed and empirical models for all the above response measures were formulated. Confirmatory tests and analysis of variance results confirmed the accuracy of the model. Binder ratio was found to be the most significant parameter affecting casting surface defects and surface roughness. This was followed by pouring height and in-gate length.


2020 ◽  
Vol 14 ◽  
Author(s):  
Keerti Tiwari

: Multiple-input multiple-output (MIMO) systems have been endorsed to enable future wireless communication requirements. The efficient system designing appeals an appropriate channel model, that considers all the dominating effects of wireless environment. Therefore, some complex or less analytically acquiescent composite channel models have been proposed typically for single-input single-output (SISO) systems. These models are explicitly employed for mobile applications, though, we need a specific study of a model for MIMO system which can deal with radar clutters and different indoor/outdoor and mobile communication environments. Subsequently, the performance enhancement of MIMO system is also required in such scenario. The system performance enhancement can be examined by low error rate and high capacity using spatial diversity and spatial multiplexing respectively. Furthermore, for a more feasible and practical system modeling, we require a generalized noise model along with a composite channel model. Thus, all the patents related to MIMO channel models are revised to achieve the near optimal system performance in real world scenario. This review paper offers the methods to improve MIMO system performance in less and severe fading as well as shadowing environment and focused on a composite Weibull-gamma fading model. The development is the collective effects of selecting the appropriate channel models, spatial multiplexing/detection and spatial diversity techniques both at the transmitter and the receivers in the presence of arbitrary noise.


2019 ◽  
Vol 19 (10) ◽  
pp. 6746-6749 ◽  
Author(s):  
Taejin Jang ◽  
Myung-Hyun Baek ◽  
Min-Woo Kwon ◽  
Sungmin Hwang ◽  
Jeesoo Chang ◽  
...  

Silicon ◽  
2021 ◽  
Author(s):  
G. Sujatha ◽  
N. Mohankumar ◽  
R. Poornachandran ◽  
R. Saravana Kumar ◽  
Girish Shankar Mishra ◽  
...  

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.


Author(s):  
Md. Rokib Hasan ◽  
Md. Rabiul Islam ◽  
Tanjim Masroor Bhuiyan ◽  
Muhib Ashraf Nibir ◽  
Md. Emran Hasan ◽  
...  
Keyword(s):  

1986 ◽  
Vol 22 (7) ◽  
pp. 1129-1138 ◽  
Author(s):  
Nobuyuki Tamai ◽  
Takashi Asaeda ◽  
Hirokazu Ikeda

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