Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture

2005 ◽  
Author(s):  
Zhi Ye ◽  
R.K. Satzoda ◽  
U. Sharma ◽  
N. Nazimudeen ◽  
Chip-Hong Chang
Keyword(s):  
Performance Evaluation ◽  
Fir Filter ◽  
Direct Form ◽  
Merged Arithmetic

scholarly journals Design of Variable Fractional Delay Filter using FIR Filter Approximation

2019 ◽  
Vol 8 (4) ◽  
pp. 5932-5936
Keyword(s):  
Interpolation Method ◽  
Fir Filter ◽  
Beam Forming ◽  
Rf Signals ◽  
Direct Form ◽  
Fractional Delay ◽  
Filter Approximation ◽  
Fractional Delay Filter ◽  
Is Design

Beamforming plays an important role in the field of wireless communication. Beamforming means combination of a radio frequency (RF) signals from multiple antennas to form a single direction beam. This technique improves the quality of communication and reduces the interference of signal. In beam forming technique, different phases signals can be achieved with different signals and the received phase delay signals are converted into same phase, multiply with weight factor and combined this signals to form a beam in desired direction. The required phase delays are generated by using a Variable fractional delay filter. Variable fractional delay filter is design by using a direct form of a FIR filter structure. Variable fractional delay filter is calculated by two different phase signals from digital antennas and those two different phase signals are converted to in- phase and added together to form a beam forming. As the order of the filter increases, the delay also increases. The filter coefficients of the variable fractional delay filter are calculated my using a Lagrange interpolation method. The variable fractional delay filter is designed by using software Xilinx version 14.3

scholarly journals PERFORMANCE EVALUATION OF BOOTH AND WALLACE MULTIPLIER USING FIR FILTER

2013 ◽  
pp. 170-174
Author(s):  
H. RAGHUNATHA RAO ◽  
T. ASHOK KUMAR ◽  
N.SURESH BABU
Keyword(s):  
Performance Evaluation ◽  
Fir Filter ◽  
Filter Performance

An area-and speed efficient multipliers is proposed in the thesis. the proposed booth and Wallace multipliers shows the tradeoff in the performance evaluation for the fir filter applications. For implementation of fir filter in this paper the adders introduced are carry save adder and carry skip adder. For evaluating the fir filter performance the tested combinations are booth carry save , booth carry skip , Wallace carry save , Wallace carry skip.

scholarly journals Optimization of Arithmetical Operators for the Enhanced Wallace Stage

2018 ◽  
Vol 9 (3) ◽  
pp. 591
Author(s):  
K. Gugan ◽  
S. V. Saravanan
Keyword(s):  
Signal Processing ◽  
Digital Signal ◽  
Full Adder ◽  
Fir Filter ◽  
Digital Form ◽  
Multiplication Process ◽  
Initial Stage ◽  
Direct Form ◽  
Two Stages ◽  
Wallace Tree Multiplier

<p>In the field of Digital signal processing (DSP), the reduction of some logical elements counts is one of the main considerations. To minimize the area, computational delay, and power, the digital form FIR filter is to be implemented. The optimization of the ATP (Area, Time and Power) is achieved by using the efficient multiplication and accumulation unit (MAC). In this work, the direct form FIR filter with the efficient MAC unit is presented. At the initial stage, the half adders and full adders are to be modified by the reduction of the logical gates. The modified half and full adder are implemented in the Wallace tree multiplier for performing the efficient multiplication process. Carry save adder is divided into the two stages to reduce the computational delay of arithmetical operators. The proposed MAC design is implemented in the direct form FIR filter by using the HDL language.</p>

Dynamic Partial Reconfiguration with FIR Filter Application

2015 ◽  
Vol 4 (3) ◽  
pp. 201
Author(s):  
Noopur Astik
Keyword(s):  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Pass Filter ◽  
Direct Form ◽  
Field Programmable ◽  
Low Pass ◽  
High Pass

Dynamic partial reconfiguration has evolved as a very prominent state of art for efficient area utilization of <em>Field Programmable Gate Array</em> (FPGA) as well as significant reduction in its overall power consumption when properly used to lessen the idle logic on FPGA. It provides desired results even as the computational complexity increases in the field of Digital Signal Processing. This paper explains Dynamic Partial Reconfiguration (DPR) with an example of Finite Impulse response (FIR) filter of order 10. Initially RTL coding for Direct Form FIR structure is written in Verilog in fixed point format for low pass and high pass filter modules using ISE Design suite. Functioning of the both the modules is verified individually through hardware co-simulation on ZYBO (Zynq Board) from Digilent using Black Box from System Generator. Finally dynamic partial reconfigurable FIR filter with low pass and high pass as reconfigurable modules is implemented on ZYBO using PlanAhead tool. Final comparison of resource utilization with and without DPR is presented

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