High level synthesis using Vivado HLS for Zynq SoC: Image processing case studies

2016 ◽  
Author(s):  
A. Cortes ◽  
I. Velez ◽  
A. Irizar
Keyword(s):  
Image Processing ◽  
Case Studies ◽  
High Level Synthesis ◽  
High Level ◽  
Vivado Hls

scholarly journals Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

10.29007/x3tx ◽  
2019 ◽  
Author(s):  
Luka Daoud ◽  
Fady Hussein ◽  
Nader Rafla
Keyword(s):  
High Level Synthesis ◽  
Advanced Encryption Standard ◽  
Data Confidentiality ◽  
Maximum Throughput ◽  
Loop Unrolling ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
High Level ◽  
Dedicated Hardware ◽  
Vivado Hls

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

AN EFFICIENT FPGA OVERLAY FOR COLOR TRANSFORMATION FUNCTION USING HIGH LEVEL SYNTHESIS

2021 ◽  
Vol 9 (1) ◽  
pp. 280-287
Author(s):  
Minal Deshmukh, Prasad Khandekar, Nishikant Sadafale
Keyword(s):  
Image Processing ◽  
Real Time ◽  
Transformation Function ◽  
High Level Synthesis ◽  
Smart Devices ◽  
Real Time Image Processing ◽  
Real Time Image ◽  
Color Transformation ◽  
High Level ◽  
Time Image

Image Processing is a significantly desirable in commercial, industrial, and medical applications. Processor based architectures are inappropriate for real time applications as Image processing algorithms are quite intensive in terms of computations. To reduce latency and limitation in performance due to limited amount of memory and fixed clock frequency for synthesis in processor-based architecture, FPGA can be used in smart devices for implementing real time image processing applications. To increase speed of real time image processing custom overlays (Hardware Library of programmable logic circuit) can be designed to run on FPGA fabric. The IP core generated by the HLS (High Level Synthesis) can be implemented on a reconfigurable platform which allows effective utilization of channel bandwidth and storage. In this paper we have presented FPGA overlay design for color transformation function using Xilinx’s python productivity board PYNQ-Z2 to get benefit in performance over a traditional processor. Performance comparison of custom overlay on FPGA and Processor based platform shows FPGA execution yields minimum computation time.

scholarly journals A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator

Technologies ◽  
2018 ◽  
Vol 7 (1) ◽  
pp. 4
Author(s):  
Dimitris Tsiktsiris ◽  
Dimitris Ziouzios ◽  
Minas Dasygenis
Keyword(s):  
Image Processing ◽  
Edge Detection ◽  
Digital Image Processing ◽  
Digital Image ◽  
High Level Synthesis ◽  
Bare Metal ◽  
Sobel Edge Detection ◽  
High Level ◽  
Graphics Processing ◽  
Better Than

Most frequently, an FPGA is used as an implementation platform in applications of graphics processing, as its structure can effectively exploit both spatial and temporal parallelism. Such parallelization techniques involve fundamental restrictions, namely being their dependence on both the processing model and the system’s hardware constraints, that can force the designer to restructure the architecture and the implementation. Predesigned accelerators can significantly assist the designer to solve this problem and meet his deadlines. In this paper, we present our accelerators for Grayscale and Sobel Edge Detection, two of the most fundamental algorithms used in digital image processing projects. We have implemented those algorithms with a “bare-metal” VHDL design, written purely by hand, as a portable USB accelerator device, as well as an HLS-based overlay of a similar implementation designed to be used by a Python interface. The comparisons of the two architectures showcase that the HLS generated design can perform equally to or even better than the handwritten HDL equivalent, especially when the correct compiler directives are provided.

scholarly journals High-Level Synthesis of Online K-Means Clustering Hardware for a Real-Time Image Processing Pipeline

2019 ◽  
Vol 5 (3) ◽  
pp. 38 ◽  
Author(s):  
Aiman Badawi ◽  
Muhammad Bilal
Keyword(s):  
Image Processing ◽  
Image Segmentation ◽  
Real Time ◽  
Moving Average ◽  
Weighted Average ◽  
High Level Synthesis ◽  
Hardware Accelerator ◽  
Hardware Complexity ◽  
Processing Pipeline ◽  
High Level

The growing need for smart surveillance solutions requires that modern video capturing devices to be equipped with advance features, such as object detection, scene characterization, and event detection, etc. Image segmentation into various connected regions is a vital pre-processing step in these and other advanced computer vision algorithms. Thus, the inclusion of a hardware accelerator for this task in the conventional image processing pipeline inevitably reduces the workload for more advanced operations downstream. Moreover, design entry by using high-level synthesis tools is gaining popularity for the facilitation of system development under a rapid prototyping paradigm. To address these design requirements, we have developed a hardware accelerator for image segmentation, based on an online K-Means algorithm using a Simulink high-level synthesis tool. The developed hardware uses a standard pixel streaming protocol, and it can be readily inserted into any image processing pipeline as an Intellectual Property (IP) core on a Field Programmable Gate Array (FPGA). Furthermore, the proposed design reduces the hardware complexity of the conventional architectures by employing a weighted instead of a moving average to update the clusters. Experimental evidence has also been provided to demonstrate that the proposed weighted average-based approach yields better results than the conventional moving average on test video sequences. The synthesized hardware has been tested in real-time environment to process Full HD video at 26.5 fps, while the estimated dynamic power consumption is less than 90 mW on the Xilinx Zynq-7000 SOC.

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