LOEDAR: A low cost error detection and recovery scheme for ECC

2011 ◽  
Author(s):  
Kun Ma ◽  
Kaijie Wu
Keyword(s):  
Error Detection ◽  
Low Cost ◽  
Recovery Scheme

Setting an error detection infrastructure with low cost acoustic wave detectors

2012 ◽  
Vol 40 (3) ◽  
pp. 333-343 ◽  
Author(s):  
Gaurang Upasani ◽  
Xavier Vera ◽  
Antonio González
Keyword(s):  
Acoustic Wave ◽  
Error Detection ◽  
Low Cost

Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors

2014 ◽  
Author(s):  
Jian Fu ◽  
Qiang Yang ◽  
Raphael Poss ◽  
Chris R. Jesshope ◽  
Chunyuan Zhang
Keyword(s):  
Low Cost ◽  
Fault Recovery ◽  
Multithreaded Processors ◽  
Transient Fault ◽  
Recovery Scheme

scholarly journals Exploiting Existing Comparators for Fine-Grained Low-Cost Error Detection

2014 ◽  
Vol 11 (3) ◽  
pp. 1-24
Author(s):  
Gulay Yalcin ◽  
Oguz Ergin ◽  
Emrah Islek ◽  
Osman Sabri Unsal ◽  
Adrian Cristal
Keyword(s):  
Error Detection ◽  
Low Cost ◽  
Fine Grained

scholarly journals An Efficient Hardware-Based Fault-Tolerant Method for SMS4

2018 ◽  
Vol 208 ◽  
pp. 02005
Author(s):  
Hanguang Luo ◽  
Guangjun Wen ◽  
Jian Su
Keyword(s):  
Error Detection ◽  
Wireless Lan ◽  
Fault Tolerant ◽  
Low Cost ◽  
Primary Objective ◽  
Data Confidentiality ◽  
Detection Scheme ◽  
Detection Delay ◽  
Encryption Decryption ◽  
Online Error Detection

The SMS4 cryptosystem has been used in the Wireless LAN Authentication and Privacy Infrastructure (WAPI) standard for providing data confidentiality in China. So far, reliability has not been considered a primary objective in original version. However, a single fault in the encryption/decryption process can completely change the result of the cryptosystem no matter the natural or malicious injected faults. In this paper, we proposed low-cost structure-independent fault detection scheme for SMS4 cryptosystem which is capable of performing online error detection and can detect a single bit fault or odd multiple bit faults in coverage of 100 percent. Finally, the proposed techniques have been validated on Virtex-7 families FPGA platform to analyze its power consumption, overhead and time delay. It only needs 85 occupied Slices and 8.72mW to run a fault-tolerant scheme of SMS4 cryptosystem with 0.735ns of detection delay. Our new scheme increases in minimum redundancy to enhance cryptosystem’s reliability and achieve a better performance compared with the previous scheme.

An Optimized FPGA Implementation of CAN 2.0 Protocol Error Detection Circuitry

2017 ◽  
Vol 6 (3) ◽  
pp. 602
Author(s):  
Md Farukh Hashmi ◽  
Avinash G. Keskar
Keyword(s):  
Embedded System ◽  
Data Storage ◽  
Error Detection ◽  
Low Cost ◽  
Disk Drive ◽  
Critical Issue ◽  
Subsequent Treatment ◽  
Area Network ◽  
Reconfigurable Platform ◽  
Vhdl Code

Controller Area Network is an ideal serial bus design suitable for modern embedded system based networks. It finds its use in most of critical applications, where error detection and subsequent treatment on error is a critical issue. CRC (Cyclic Redundancy Check) block was developed on FPGA in order to meet the needs for simple, low power and low cost wireless communication. This paper gives a short overview of CRC block in the Digital transmitter based on the CAN 2.0 protocols. CRC is the most preferred method of encoding because it provides very efficient protection against commonly occurring burst errors, and is easily implemented. This technique is also sometimes applied to data storage devices, such as a disk drive. In this paper a technique to model the error detection circuitry of CAN 2.0 protocols on reconfigurable platform have been discussed? The software simulation results are presented in the form of timing diagram.FPGA implementation results shows that the circuitry requires very small amount of digital hardware. The Purpose of the research is to diversify the design methods by using VHDL code entry through Modelsim 5.5e simulator and Xilinx ISE8.3i.The VHDL code is used to characterize the CRC block behavior which is then simulated, synthesized and successfully implemented on Sparten3 FPGA .Here, Simulation and Synthesized results are also presented to verify the functionality of the CRC -16 Block. The data rate of CRC block is 250 kbps .Estimated power consumption and maximum operating frequency of the circuitry is also provided.

scholarly journals Low-Cost Digital Test Solution for Symbol Error Detection of RF ZigBee Transmitters

2019 ◽  
Vol 19 (1) ◽  
pp. 16-24 ◽  
Author(s):  
T. Vayssade ◽  
F. Azais ◽  
L. Latorre ◽  
F. Lefevre
Keyword(s):  
Error Detection ◽  
Low Cost ◽  
Test Solution ◽  
Digital Test

Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores

2015 ◽  
Vol 14 (1) ◽  
pp. 13-16 ◽  
Author(s):  
Ralph Nathan ◽  
Daniel J. Sorin
Keyword(s):  
Error Detection ◽  
Low Cost

Exponent monitoring for low-cost concurrent error detection in FPU control logic

2011 ◽  
Author(s):  
Michail Maniatakos ◽  
Yiorgos Makris ◽  
Prabhakar Kudva ◽  
Bruce Fleischer
Keyword(s):  
Error Detection ◽  
Low Cost ◽  
Concurrent Error Detection ◽  
Control Logic
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