A novel tag access scheme for low power L2 cache

2011 Design, Automation & Test in Europe ◽

10.1109/date.2011.5763108 ◽

2011 ◽

Cited By ~ 1

Author(s):

Hyunsun Park ◽

Sungjoo Yoo ◽

Sunggu Lee

Keyword(s):

Low Power ◽

Access Scheme ◽

L2 Cache

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Low-power consumption spacial group based random access scheme for MTC devices

2017 IEEE/CIC International Conference on Communications in China (ICCC) ◽

10.1109/iccchina.2017.8330512 ◽

2017 ◽

Author(s):

Zhenya Shao ◽

Jun Zhang ◽

Xinghua Sun ◽

Hongbo Zhu

Keyword(s):

Power Consumption ◽

Low Power ◽

Random Access ◽

Low Power Consumption ◽

Access Scheme

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Design of low power L2 cache architecture using partial way tag information

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) ◽

10.1109/icgccee.2014.6922292 ◽

2014 ◽

Author(s):

A. Divya Jebaseeli ◽

M. Kiruba

Keyword(s):

Low Power ◽

Cache Architecture ◽

L2 Cache

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A leakage-aware L2 cache management technique for producer–consumer sharing in low-power chip multiprocessors

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2011.08.006 ◽

2011 ◽

Vol 71 (12) ◽

pp. 1545-1557 ◽

Cited By ~ 3

Author(s):

Hyunhee Kim ◽

Jihong Kim

Keyword(s):

Low Power ◽

Chip Multiprocessors ◽

Management Technique ◽

Cache Management ◽

L2 Cache

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DHL‐cache: dynamic per history length adjustment for low‐power L2 cache

Electronics Letters ◽

10.1049/el.2016.1465 ◽

2016 ◽

Vol 52 (15) ◽

pp. 1297-1298

Author(s):

H.W. Joo ◽

E.Y. Chung

Keyword(s):

Low Power ◽

L2 Cache

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DCW-MAC: An Energy Efficient Medium Access Scheme Using Duty-Cycled Low-Power Wake-Up Receivers

2011 IEEE Vehicular Technology Conference (VTC Fall) ◽

10.1109/vetecf.2011.6093231 ◽

2011 ◽

Cited By ~ 9

Author(s):

Nafiseh Seyed Mazloum ◽

Ove Edfors

Keyword(s):

Low Power ◽

Energy Efficient ◽

Medium Access ◽

Access Scheme

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A Multistep Tag Comparison Method for a Low-Power L2 Cache

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2011.2177458 ◽

2012 ◽

Vol 31 (4) ◽

pp. 559-572 ◽

Cited By ~ 9

Author(s):

Hyunsun Park ◽

Sungjoo Yoo ◽

Sunggu Lee

Keyword(s):

Low Power ◽

Comparison Method ◽

L2 Cache

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Low-power L2 cache design for multi-core processors

Electronics Letters ◽

10.1049/el.2010.0642 ◽

2010 ◽

Vol 46 (9) ◽

pp. 618

Author(s):

C.-M. Chung ◽

J. Kim

Keyword(s):

Low Power ◽

L2 Cache ◽

Cache Design

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Low power L2 cache design using partially tagged bloom filter and hotline check

2013 International Conference on Computer Communication and Informatics ◽

10.1109/iccci.2013.6466306 ◽

2013 ◽

Author(s):

Sharon Mathew ◽

M Jagadeeswari

Keyword(s):

Low Power ◽

Bloom Filter ◽

L2 Cache ◽

Cache Design

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A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503677 ◽

2016 ◽

Cited By ~ 4

Author(s):

Masami Nakajima ◽

Ichiro Naka ◽

Fumihiro Matsushima ◽

Tadaaki Yamauchi

Keyword(s):

Low Power ◽

Memory Access ◽

Access Scheme

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Ultra Low Power Bioelectronics

10.1017/cbo9780511841446 ◽

2009 ◽

Cited By ~ 187

Author(s):

Rahul Sarpeshkar

Keyword(s):

Low Power ◽

Ultra Low Power

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