Low-power L2 cache design for multi-core processors

2010 ◽  
Vol 46 (9) ◽  
pp. 618
Author(s):  
C.-M. Chung ◽  
J. Kim
Keyword(s):  
Low Power ◽  
L2 Cache ◽  
Cache Design

Cache Design for Low Power and High Yield

2008 ◽  
Author(s):  
Baker Mohammad ◽  
Martin Saint-Laurent ◽  
Paul Bassett ◽  
Jacob Abraham
Keyword(s):  
Low Power ◽  
High Yield ◽  
Cache Design

Low power instruction cache design based on branch execution tracks

2013 ◽  
Author(s):  
Quanquan Li ◽  
Qi Wang ◽  
Tiejun Zhang ◽  
Donghui Wang ◽  
Chaohuan Hou
Keyword(s):  
Low Power ◽  
Instruction Cache ◽  
Cache Design

DHL‐cache: dynamic per history length adjustment for low‐power L2 cache

2016 ◽  
Vol 52 (15) ◽  
pp. 1297-1298
Author(s):  
H.W. Joo ◽  
E.Y. Chung
Keyword(s):  
Low Power ◽  
L2 Cache
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