Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking

2008 ◽  
Author(s):  
Yang Qu ◽  
Juha-Pekka Soininen ◽  
Jari Nurmi
Keyword(s):  
Reconfigurable Devices ◽  
Run Time

Methodology for Implementing Scalable Run-Time Reconfigurable Devices

2011 ◽  
Vol 57 (2) ◽  
pp. 177-183 ◽  
Author(s):  
Łukasz Kotynia ◽  
Piotr Amrozik ◽  
Andrzej Napieralski
Keyword(s):  
Dynamically Reconfigurable ◽  
Fine Grained ◽  
Operating Modes ◽  
Reconfigurable Devices ◽  
Multiple Data ◽  
Implementation Techniques ◽  
Field Programmable ◽  
Reconfigurable Processing ◽  
Run Time ◽  
Implementation Methodology

Methodology for Implementing Scalable Run-Time Reconfigurable Devices The aim of this paper is to present the implementation methodology for an ASIC constituting the fine-grained array of dynamically reconfigurable processing elements. This methodology was developed during the work on a device which can operate as a typical Field Programmable Gate Array (FPGA) with some bio-inspired features or as a multi-core Single Instruction Multiple Data (SIMD) processor. Such high diversity of possible operating modes makes the design implementation extremely demanding. As a consequence, the comprehensive study and analysis of the different possible implementation techniques in this case allowed us to formulate a consistent and complete methodology that can be applied to other systems of similar structure.

COMPLETE AND APPROXIMATE METHODS FOR OFF-LINE PLACEMENT OF HARDWARE TASKS ON RECONFIGURABLE DEVICES

2013 ◽  
Vol 22 (02) ◽  
pp. 1250080 ◽  
Author(s):  
IKBEL BELAID ◽  
BASSEM OUNI ◽  
FABRICE MULLER ◽  
MAHER BENJEMAA
Keyword(s):  
Resource Efficiency ◽  
Bees Algorithm ◽  
Mixed Integer ◽  
Analytic Method ◽  
Partial Reconfiguration ◽  
Approximate Methods ◽  
Reconfigurable Devices ◽  
Line Placement ◽  
Run Time ◽  
Task Placement

With the advent of run-time partial reconfiguration, the most recent reconfigurable devices support reconfiguring hardware tasks individually, without interrupting the remaining tasks running on the same device. While the concept of run-time partial reconfiguration increases performance and resource utilization, it also leads to resource wastage, high configuration overhead and complex allocation situations of hardware tasks on reconfigurable devices. Many on-line and off-line methods for hardware task placement have been proposed for such reconfigurable devices to enhance placement quality expressed by fragmentation rate, the amount of task rejection and a few of them also estimate configuration overhead. However, these works treat each criterion individually and therefore do not reflect the overall metrics of placement quality. Hardware task placement is a multi-objective combinatory optimization problem. In this paper, we investigate the problem of off-line placement of hardware tasks in partially reconfigurable devices and we present a new three-level resource management that is based on two methods, i.e., a complete analytic method: the formulation into mixed integer programming, and an approximate iterative method: the Bees algorithm. For both methods, the placement quality is measured by the rate of resource efficiency and by the amount of configuration overhead. Experiments demonstrate that the analytic method provides better resource efficiency than the Bees Algorithm by 33% and attains 15% of gain in configuration overhead.

Compiler-Aided Run-Time Performance Speed-Up in Super-Scalar Processor

10.28945/3391 ◽  
2009 ◽  
Author(s):  
Moshe Pelleh
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
General Purpose ◽  
Experimental Results ◽  
Medium Size ◽  
Organic System ◽  
Software Application ◽  
Organic Systems ◽  
Special Cases ◽  
Run Time

In our world, where most systems become embedded systems, the approach of designing embedded systems is still frequently similar to the approach of designing organic systems (or not embedded systems). An organic system, like a personal computer or a work station, must be able to run any task submitted to it at any time (with certain constrains depending on the machine). Consequently, it must have a sophisticated general purpose Operating System (OS) to schedule, dispatch, maintain and monitor the tasks and assist them in special cases (particularly communication and synchronization between them and with external devices). These OSs require an overhead on the memory, on the cache and on the run time. Moreover, generally they are task oriented rather than machine oriented; therefore the processor's throughput is penalized. On the other hand, an embedded system, like an Anti-lock Braking System (ABS), executes always the same software application. Frequently it is a small or medium size system, or made up of several such systems. Many small or medium size embedded systems, with limited number of tasks, can be scheduled by our proposed hardware architecture, based on the Motorola 500MHz MPC7410 processor, enhancing its throughput and avoiding the software OS overhead, complexity, maintenance and price. Encouraged by our experimental results, we shall develop a compiler to assist our method. In the meantime we will present here our proposal and the experimental results.

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