Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling

2007 ◽  
Author(s):  
Quming Zhou ◽  
Kedarnath J. Balakrishnan
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Cost Reduction ◽  
Test Scheduling ◽  
Combined Approach ◽  
Test Data Compression ◽  
Test Cost ◽  
Test Cost Reduction

Test cost reduction for logic circuits: Reduction of test data volume and test application time

2005 ◽  
Vol 36 (6) ◽  
pp. 69-83 ◽  
Author(s):  
Yoshinobu Higami ◽  
Seiji Kajihara ◽  
Hideyuki Ichihara ◽  
Yuzo Takamatsu
Keyword(s):  
Test Data ◽  
Cost Reduction ◽  
Logic Circuits ◽  
Application Time ◽  
Test Cost ◽  
Test Application Time ◽  
Test Cost Reduction ◽  
Test Application ◽  
Data Volume

Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs

2011 ◽  
pp. 434-459
Author(s):  
Anders Larsson ◽  
Urban Ingelsson ◽  
Erik Larsson ◽  
Krishnendu Chakrabarty
Keyword(s):  
Data Compression ◽  
Design Process ◽  
Test Data ◽  
Architecture Design ◽  
Test Data Compression ◽  
Compression Technique ◽  
Test Cost ◽  
Test Execution ◽  
Data Volume ◽  
Test Architecture

Test-data volume and test execution times are both costly commodities. To reduce the cost of test, previous studies have used test-data compression techniques on system-level to reduce the test-data volume or employed test architecture design for module-based SOCs to enable test schedules with low test execution time. Research on combining the two approaches is lacking. Therefore, this chapter studies how core-level test-data compression can be combined with test architecture design to reduce test cost further. The study is conducted in three steps. The first step analyzes how the TAM width influences three test-data compression techniques, namely Selective Encoding, Vector Repeat and the combination of the two. The second step investigates in what order to consider test architecture and test-data compression in the SOC design process to best reduce test cost. It is observed that test architecture design and test-data compression-technique selection should be performed in an integrated process. The third step presents a novel approach to integrate test-data compression-technique selection in the test architecture design process. Experiments on benchmarks with realistic cores show that the integrated approach achieves up to 32% reduction in test cost (7.8% on average) compared to non-integrated test architecture design and test-data compression technique selection.

A Test Data Compression Scheme Based on Mixed Fixed and Variable Length Coding

2009 ◽  
Vol 31 (10) ◽  
pp. 1826-1834 ◽  
Author(s):  
Wen-Fa ZHAN ◽  
Hua-Guo LIANG ◽  
Feng SHI ◽  
Zheng-Feng HUANG
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Variable Length ◽  
Test Data Compression ◽  
Compression Scheme ◽  
Variable Length Coding

Test data compression of system-on-a-chip (SoC) based on partial runs reversing

2010 ◽  
Vol 24 (1) ◽  
pp. 23-28
Author(s):  
Yiming Ouyang ◽  
Baosheng Zou ◽  
Huaguo Liang ◽  
Xi’e Huang
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Test Data Compression ◽  
System On A Chip

Test data compression technique based on partial data block reuse in SoC

2010 ◽  
Vol 24 (5) ◽  
pp. 487-493
Author(s):  
Yiming Ouyang ◽  
Xi'e Huang ◽  
Huaguo Liang ◽  
Baosheng Zou
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Data Block ◽  
Test Data Compression ◽  
Compression Technique ◽  
Partial Data

Reduced-Pin-Count BOST for Test-Cost Reduction

2021 ◽  
pp. 1-1
Author(s):  
Youngkwang Lee ◽  
Young-woo Lee ◽  
Sungyoul Seo ◽  
Sungho Kang
Keyword(s):  
Cost Reduction ◽  
Test Cost ◽  
Test Cost Reduction
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