Smart Bit-width Allocation for Low Power Optimization in a SystemC based ASIC Design Environment

2006 ◽  
Author(s):  
A. Mallik ◽  
D. Sinha ◽  
P. Banerjee ◽  
Hai Zhou
Keyword(s):  
Low Power ◽  
Power Optimization ◽  
Design Environment ◽  
Asic Design

scholarly journals Exploration of dual supply voltage logic synthesis in state-of-the-art ASIC design flows

2003 ◽  
Vol 1 ◽  
pp. 185-189
Author(s):  
T. Mahnke ◽  
W. Stechele ◽  
M. Embacher ◽  
W. Hoeld
Keyword(s):  
Power Optimization ◽  
Supply Voltage ◽  
State Of The Art ◽  
Logic Synthesis ◽  
Design Environment ◽  
New Approach ◽  
Cell Library ◽  
Asic Design ◽  
Synthesis Methodology ◽  
Basic Evaluation

Abstract. Dual supply voltage scaling (DSVS) for logiclevel power optimization at the has increasingly attracted attention over the last few years. However, mainly due to the fact that the most widely used design tools do not support this new technique, it has still not become an integral part of real-world design flows. In this paper, a novel logic synthesis methodology that enables DSVS while relying entirely on standard tools is presented. The key to this methodology is a suitably modeled dual supply voltage (DSV) standard cell library. A basic evaluation of the methodology has been carried out on a number of MCNC benchmark circuits. In all these experiments, the results of state-of-the-art powerdriven single supply voltage (SSV) logic synthesis have been used as references in order to determine the true additional benefit of DSVS. Compared with the results of SSV power optimization, additional power reductions of 10% on average have been achieved. The results prove the feasibility of the new approach and reveal its greater efficiency in comparison with a well-known dedicated DSVS algorithm. Finally, the methodology has been applied to an embedded microcontroller core in order to further explore the potentials and limitations of DSVS in an existing industrial design environment.

The CMOS gate forest: an efficient and flexible high-performance ASIC design environment

10.1109/4.999 ◽  
1988 ◽  
Vol 23 (2) ◽  
pp. 387-399 ◽  
Author(s):  
M.A. Beunder ◽  
J.P. Kernhof ◽  
B. Hoefflinger
Keyword(s):  
High Performance ◽  
Design Environment ◽  
Asic Design

scholarly journals Low Power Design for ASIC Cores

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Clock Gating ◽  
Asic Design ◽  
Design Techniques

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium

2020 ◽  
Vol 67 (11) ◽  
pp. 2682-2686
Author(s):  
J. M. Mora-Gutierrez ◽  
C. J. Jimenez-Fernandez ◽  
M. Valencia-Barrero
Keyword(s):  
Low Power ◽  
Asic Design
Sign in / Sign up

Export Citation Format

Share Document