Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding

Author(s):  
X. Kavousianos ◽  
E. Kalligeros ◽  
D. Nikolos
Author(s):  
Sanjoy Mitra ◽  
Debaprasad Das

As system-on-chip (SoC) integration is growing very rapidly, increased circuit densities in SoC have lead a radical increase in test data volume and reduction of this large test data volume is one of the biggest challenges in the testing industry. This paper presents an efficient test independent compression scheme primarily based on the error correcting Hamming codes. The scheme operates on the pre-computed test data without the need of structural information of the circuit under test and thus it is applicable for IP cores in SoC. Test vectors are equally sliced into the size of ‘<em>n’</em> bits. Individual slices are treated as a Hamming codeword consisting of ‘<em>p’</em> parity bits and ‘<em>d’</em> data bits (<em>n = d + p)</em> and validity of each codeword is verified. If a valid slice is encountered<em>’</em> data bits prefixed by ‘<em>1’</em> are written to the compressed file, while for a non-valid slice all ‘<em>n’</em> bits preceded by ‘<em>0’</em> are written to the compressed file. Finally, we apply Huffman coding and RLE in order to improve the compression ratio further The efficiency of the proposed hybrid scheme is verified with the experimental outcomes and comparisons to existing compression methods suitable for testing of IP cores.


Author(s):  
Xrysovalantis Kavousianos ◽  
Emmanouil Kalligeros ◽  
Dimitris Nikolos

2012 ◽  
Vol 38 ◽  
pp. 680-684
Author(s):  
S. Saravanan ◽  
R. Vijay Sai ◽  
A. Balasubramaniyan ◽  
R. Silambamuthan ◽  
G. Dinesh Babu ◽  
...  

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-9 ◽  
Author(s):  
Usha S. Mehta ◽  
Kankar S. Dasgupta ◽  
Niranjan M. Devashrayee

The run length based coding schemes have been very effective for the test data compression in case of current generation SoCs with a large number of IP cores. The first part of paper presents a survey of the run length based codes. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In the second part of the paper, the five different approaches for “don't care” bit filling based on nature of runs are proposed to predict the maximum compression based on entropy. Here the various run length based schemes are compared with maximum data compression limit based on entropy bounds. The actual compressions claimed by the authors are also compared. For various ISCAS circuits, it has been shown that when the X filling is done considering runs of zeros followed by one as well as runs of ones followed by zero (i.e., Extended FDR), it provides the maximum data compression. In third part, it has been shown that the average test power and peak power is minimum when the don't care bits are filled to make the long runs of 0s as well as 1s.


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