Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.243899 ◽

2006 ◽

Cited By ~ 13

Author(s):

F. Balarin ◽

R. Passerone

Keyword(s):

Functional Verification ◽

Interface Specification ◽

Formal Interface ◽

Verification Methodology

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Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761162 ◽

2003 ◽

Cited By ~ 12

Author(s):

L. Fournier ◽

Y. Arbetman ◽

M. Levinger

Keyword(s):

Functional Verification ◽

Test Program ◽

Verification Methodology ◽

Program Generator

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Efficient system-level functional verification methodology for multimedia applications

IEEE Design & Test of Computers ◽

10.1109/mdt.2003.1188263 ◽

2003 ◽

Vol 20 (2) ◽

pp. 56-64 ◽

Cited By ~ 3

Author(s):

M. Cupak ◽

F. Catthoor ◽

H.J. De Man

Keyword(s):

Multimedia Applications ◽

System Level ◽

Functional Verification ◽

Efficient System ◽

Verification Methodology

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Semi-formal and formal interface specification for system of systems architecture

2013 IEEE International Systems Conference (SysCon) ◽

10.1109/syscon.2013.6549946 ◽

2013 ◽

Cited By ~ 16

Author(s):

Jeremy Bryans ◽

R. Payne ◽

J. Holt ◽

S. Perry

Keyword(s):

System Of Systems ◽

Systems Architecture ◽

Interface Specification ◽

Formal Interface

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Functional verification methodology of Chameleon processor

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545613 ◽

2005 ◽

Cited By ~ 3

Author(s):

F. Casaubieilh ◽

A. McIsaac ◽

M. Benjamin ◽

M. Bartley ◽

F. Pogodalla ◽

...

Keyword(s):

Functional Verification ◽

Verification Methodology

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Functional verification methodology using Hierarchical Coloured Petri Nets-based testbenches

2008 IEEE International Conference on Systems, Man and Cybernetics ◽

10.1109/icsmc.2008.4811600 ◽

2008 ◽

Author(s):

Cassio L. Rodrigues ◽

Fabio J. Morais ◽

Leandro M. L. Silva ◽

Karina R. G. da Silva ◽

Jorge C. A. de Figueiredo ◽

...

Keyword(s):

Petri Nets ◽

Functional Verification ◽

Coloured Petri Nets ◽

Verification Methodology

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External Memory Interface Verification Based on VMM

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.981.103 ◽

2014 ◽

Vol 981 ◽

pp. 103-106

Author(s):

Rui Xu ◽

Zhan Peng Jiang ◽

Chang Chun Dong ◽

Xue Bin Lu

Keyword(s):

Complex Function ◽

External Memory ◽

Functional Verification ◽

Verification Method ◽

Coverage Control ◽

Memory Interface ◽

Verification Methodology

With the growth of the scale of SoC, function verification becomes more and more complicated. Traditional functional verification method is confronted with some challenges. This paper achieves coverage-driven, constrained-randomization and assertion verification methodology based on SystemVerilog and VMM, to build verification platform by taking example of EMI (external memory interface). As result of verification, we can monitor coverage, control the platform, optimize testbench and testcase, finish function coverage 100%. These applications can simplify complex function verification, improve the platform reuse, and meet the needs of chip verification.

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