Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors

2006 ◽  
Author(s):  
S. Eyerman ◽  
L. Eeckhout ◽  
K. De Bosschere
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Efficient Design

scholarly journals Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-20
Author(s):  
Gongyu Wang ◽  
Greg Stitt ◽  
Herman Lam ◽  
Alan George
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Core Level ◽  
Prediction Methods ◽  
Clock Frequency ◽  
Worst Case ◽  
Model Based ◽  
Dsp Applications

Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many high-performance computing and embedded applications. However, unlike software design tools, the relatively immature state of FPGA tools significantly limits productivity and consequently prevents widespread adoption of the technology. For example, the lengthy design-translate-execute (DTE) process often must be iterated to meet the application requirements. Previous works have enabled model-based, design-space exploration to reduce DTE iterations but are limited by a lack of accurate model-based prediction of key design parameters, the most important of which is clock frequency. In this paper, we present a core-level modeling and design (CMD) methodology that enables modeling of FPGA applications at an abstract level and yet produces accurate predictions of parameters such as clock frequency, resource utilization (i.e., area), and latency. We evaluate CMD’s prediction methods using several high-performance DSP applications on various families of FPGAs and show an average clock-frequency prediction error of 3.6%, with a worst-case error of 20.4%, compared to the best of existing high-level prediction methods, 13.9% average error with 48.2% worst-case error. We also demonstrate how such prediction enables accurate design-space exploration without coding in a hardware-description language (HDL), significantly reducing the total design time.

A Fast Design Space Exploration Method for Reconfigurable Architecture Based on Loop Optimization

2011 ◽  
Vol 467-469 ◽  
pp. 812-817 ◽  
Author(s):  
Dan Zhang ◽  
Rong Cai Zhao ◽  
Lin Han ◽  
Wei Fang Liang ◽  
Jin Qu ◽  
...  
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
General Purpose ◽  
Parallel Execution ◽  
Data Reuse ◽  
Loop Optimization ◽  
Fpga Chip ◽  
The Times

Using FPGA for general-purpose computation has become a hot research topic in high-performance computing technologies. However, the complexity of design and resource of FPGA make applying a common approach to solve the problem with mixed constraints impossible. Aiming at familiar loop structure of the applications, a design space exploration method based on FPGA hardware constrains is proposed according to the FPGA chip features, which combines the features of the corresponding application to perform loop optimization for reducing the demand of memory. Experimental results show that the method significantly improves the rate of data reuse, reduces the times of external memory access, achieves parallel execution of multiple pipelining, and effectively improves the performance of applications implemented on FPGA.

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