Tag Overflow Buffering: An Energy-Efficient Cache Architecture

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

IEEE Access ◽

10.1109/access.2021.3054021 ◽

2021 ◽

Vol 9 ◽

pp. 18915-18926

Author(s):

Young-Ho Gong

Keyword(s):

Energy Efficient ◽

Hybrid Memory ◽

Cache Architecture

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NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines

2018 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2018.8351128 ◽

2018 ◽

Author(s):

Pooneh Safayenikoo ◽

Arghavan Asad ◽

Mahmood Fathy ◽

Farah Mohammadi

Keyword(s):

Energy Efficient ◽

Chip Multiprocessors ◽

Cache Architecture

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Predictive Line Buffer: A Fast, Energy Efficient Cache Architecture

Proceedings of the IEEE SoutheastCon 2006 ◽

10.1109/second.2006.1629366 ◽

2006 ◽

Author(s):

K. Ali ◽

M. Aboelaze ◽

S. Datta

Keyword(s):

Energy Efficient ◽

Cache Architecture

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An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses

2018 IEEE Canadian Conference on Electrical & Computer Engineering (CCECE) ◽

10.1109/ccece.2018.8447736 ◽

2018 ◽

Author(s):

Pooneh Safayenikoo ◽

Arghavan Asad ◽

Farah Mohammadi

Keyword(s):

Energy Efficient ◽

Chip Multiprocessors ◽

Cache Architecture

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SLAM: High Performance and Energy Efficient Hybrid Last Level Cache Architecture for Multicore Embedded Systems

2019 IEEE International Conference on Embedded Software and Systems (ICESS) ◽

10.1109/icess.2019.8782441 ◽

2019 ◽

Author(s):

Swapnil Bhosale ◽

Sudeep Pasricha

Keyword(s):

Embedded Systems ◽

Energy Efficient ◽

High Performance ◽

Cache Architecture

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An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

IEEE Transactions on Computers ◽

10.1109/tc.2014.2378291 ◽

2015 ◽

Vol 64 (9) ◽

pp. 2460-2475 ◽

Cited By ~ 6

Author(s):

Joonho Kong ◽

Farinaz Koushanfar ◽

Sung Woo Chung

Keyword(s):

Energy Efficient ◽

Process Variation ◽

Cache Architecture

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Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture

2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips49199.2020.9097643 ◽

2020 ◽

Author(s):

Masayuki Sato ◽

Xue Hao ◽

Kazuhiko Komatsu ◽

Hiroaki Kobayashi

Keyword(s):

Energy Efficient ◽

Efficient Design ◽

Cache Architecture ◽

Hybrid Cache ◽

Energy Efficient Design

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Energy-efficient dual-port cache architecture with improved performances

Electronics Letters ◽

10.1049/el:20073037 ◽

2007 ◽

Vol 43 (1) ◽

pp. 12 ◽

Cited By ~ 4

Author(s):

X. Chen ◽

H. Bajwa

Keyword(s):

Energy Efficient ◽

Cache Architecture

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Energy-efficient cache architecture for multimedia applications

Conference, Emerging Information Technology 2005. ◽

10.1109/eitc.2005.1544355 ◽

2005 ◽

Author(s):

Chia-Lin Yang ◽

Chien-hao Lee ◽

Hung-Wei Tseng

Keyword(s):

Energy Efficient ◽

Multimedia Applications ◽

Cache Architecture

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A Fixed-point 3D Graphics Library with Energy-efficient Cache Architecture for Mobile Multimedia Systems

2005 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2005.1465657 ◽

2005 ◽

Author(s):

Min-wuk Lee ◽

Byeong-Gyu Nam ◽

Ju-Ho Sohn ◽

Namjun Cho ◽

Hyejung Kim ◽

...

Keyword(s):

Fixed Point ◽

Energy Efficient ◽

Multimedia Systems ◽

Mobile Multimedia ◽

3D Graphics ◽

Cache Architecture ◽

Graphics Library

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