Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks

2002 ◽  
Author(s):  
Zhining Huang ◽  
S. Malik
Keyword(s):  
Interconnection Networks ◽  
Dynamic Reconfiguration ◽  
Chip Design ◽  
Reconfiguration Overhead

scholarly journals Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures

2010 ◽  
Vol 2010 ◽  
pp. 1-15 ◽  
Author(s):  
Ludovic Devaux ◽  
Sana Ben Sassi ◽  
Sebastien Pillement ◽  
Daniel Chillet ◽  
Didier Demigny
Keyword(s):  
Interconnection Networks ◽  
Interconnection Network ◽  
Dynamic Reconfiguration ◽  
Computation Time ◽  
Reconfigurable Architectures ◽  
Partial Reconfiguration ◽  
Dynamic Management ◽  
Networks On Chip ◽  
Communication Architectures ◽  
On Chip

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks impacts the communications since tasks are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various communication architectures, in particular interconnection networks, are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the DRAFT network that supports the communication constraints into the context of dynamic reconfiguration. We also present DRAGOON, the automatic generator of networks, which allows to implement and to simulate the DRAFT topology. Finally, DRAFT and the two most popular Networks-on-Chip are implemented in several configurations using DRAGOON, and compared considering real implementation results.

Dynamic Reconfiguration in Planetary Exploration: A Sociomaterial Ethnography

MIS Quarterly ◽  
2014 ◽  
Vol 38 (3) ◽  
pp. 831-848 ◽  
Author(s):  
Melissa Mazmanian ◽  
◽  
Marisa Cohn ◽  
Paul Dourish ◽  
◽  
...  
Keyword(s):  
Dynamic Reconfiguration ◽  
Planetary Exploration

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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