A power reduction technique with object code merging for application specific embedded processors

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537) ◽

10.1109/date.2000.840849 ◽

2002 ◽

Cited By ~ 6

Author(s):

T. Ishihara ◽

H. Yasuura

Keyword(s):

Power Reduction ◽

Reduction Technique ◽

Embedded Processors ◽

Object Code ◽

Application Specific

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A power reduction technique with object code merging for application specific embedded processors

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343871 ◽

2000 ◽

Cited By ~ 9

Author(s):

Tohru Ishihara ◽

Hiroto Yasuura

Keyword(s):

Power Reduction ◽

Reduction Technique ◽

Embedded Processors ◽

Object Code ◽

Application Specific

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Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2014.2305012 ◽

2014 ◽

Vol 61 (4) ◽

pp. 239-243 ◽

Cited By ~ 6

Author(s):

Kang-Sub Kwak ◽

Oh-Kyong Kwon

Keyword(s):

Clock And Data Recovery ◽

Power Reduction ◽

Reduction Technique ◽

Data Recovery ◽

Single Edge ◽

Edge Tracking

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Energy-Efficient Read-Out IC for High-Precision DC Measurement System with Instrumentation Amplifier Power Reduction Technique

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401257 ◽

2021 ◽

Author(s):

Sangmin Shin ◽

Minsung Kim ◽

Junyoung Park ◽

Hyunjoong Lee ◽

Suhwan Kim

Keyword(s):

High Precision ◽

Measurement System ◽

Energy Efficient ◽

Power Reduction ◽

Reduction Technique ◽

Instrumentation Amplifier

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Design Tools for Application Specific Embedded Processors

Embedded Software - Lecture Notes in Computer Science ◽

10.1007/3-540-45828-x_24 ◽

2002 ◽

pp. 319-333 ◽

Cited By ~ 1

Author(s):

Wei Qin ◽

Subramanian Rajagopalan ◽

Manish Vachharajani ◽

Hangsheng Wang ◽

Xinping Zhu ◽

...

Keyword(s):

Embedded Processors ◽

Design Tools ◽

Application Specific

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A Computation and Power Reduction Technique for H.264 Intra Prediction

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools ◽

10.1109/dsd.2010.115 ◽

2010 ◽

Cited By ~ 1

Author(s):

Yusuf Adibelli ◽

Mustafa Parlak ◽

Ilker Hamzaoglu

Keyword(s):

Intra Prediction ◽

Power Reduction ◽

Reduction Technique

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Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits

2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI) ◽

10.1109/icoei.2019.8862751 ◽

2019 ◽

Author(s):

Ch. Narasimha Kumar ◽

A. Madhumitha ◽

N. Sesi Preetam ◽

P. Vamsi Gupta ◽

J.P. Anita

Keyword(s):

Fault Diagnosis ◽

Test Pattern ◽

Power Reduction ◽

Pattern Generation ◽

Reduction Technique ◽

Vlsi Circuits ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Test Power ◽

Test Power Reduction

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Design of Single Poly Flash Memory Cell with Power Reduction Technique at Program Mode in 65nm CMOS Process

2018 International Conference on Control, Electronics, Renewable Energy and Communications (ICCEREC) ◽

10.1109/iccerec.2018.8712096 ◽

2018 ◽

Author(s):

Chris Joseph Sagario ◽

Benjamin Quidlat ◽

Kister Genesis Jimenez ◽

Ingrid B. Escabal ◽

Allenn C. Lowaton ◽

...

Keyword(s):

Flash Memory ◽

Memory Cell ◽

Power Reduction ◽

Reduction Technique ◽

Cmos Process ◽

Flash Memory Cell ◽

Program Mode

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Analysis of peak to average power reduction technique in presence of nonlinear distortion

International Conference & Workshop on Electronics & Telecommunication Engineering (ICWET 2016) ◽

10.1049/cp.2016.1122 ◽

2016 ◽

Author(s):

S.A. Kulkarni ◽

B.K. Mishra

Keyword(s):

Nonlinear Distortion ◽

Average Power ◽

Power Reduction ◽

Reduction Technique

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A. static and dynamic energy reduction technique for I-cache and BTB in embedded processors

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337709 ◽

2005 ◽

Cited By ~ 3

Author(s):

H. Sato ◽

T. Sato

Keyword(s):

Reduction Technique ◽

Energy Reduction ◽

Embedded Processors

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No-Load Power Reduction Technique for AC/DC Adapters

IEEE Transactions on Power Electronics ◽

10.1109/tpel.2012.2185952 ◽

2012 ◽

Vol 27 (8) ◽

pp. 3685-3694 ◽

Cited By ~ 9

Author(s):

Byoung-Hee Lee ◽

Ki-Bum Park ◽

Chong-Eun Kim ◽

Gun-Woo Moon

Keyword(s):

Power Reduction ◽

Reduction Technique ◽

Load Power

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