FreezeFrame: compact test generation using a frozen clock strategy

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761214 ◽

2003 ◽

Cited By ~ 2

Author(s):

Y. Santoso ◽

M. Merten ◽

E.M. Rudnick ◽

M. Abramovici

Keyword(s):

Test Generation ◽

Compact Test

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Compact test generation for bridging faults under I/sub DDQ/ testing

Proceedings 13th IEEE VLSI Test Symposium ◽

10.1109/vtest.1995.512654 ◽

2002 ◽

Cited By ~ 17

Author(s):

R.S. Reddy ◽

I. Pomeranz ◽

S.M. Reddy ◽

S. Kajihara

Keyword(s):

Test Generation ◽

Bridging Faults ◽

Compact Test

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Automatic test generation for analog circuits using compact test transfer function models

Proceedings 10th Asian Test Symposium ◽

10.1109/ats.2001.990317 ◽

2002 ◽

Cited By ~ 2

Author(s):

B. Sahu ◽

A. Chatterjee

Keyword(s):

Transfer Function ◽

Analog Circuits ◽

Test Generation ◽

Automatic Test Generation ◽

Automatic Test ◽

Function Models ◽

Transfer Function Models ◽

Compact Test

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Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2013.2280170 ◽

2014 ◽

Vol 22 (9) ◽

pp. 1968-1979 ◽

Cited By ~ 6

Author(s):

Dong Xiang ◽

Wenjie Sui ◽

Boxue Yin ◽

Kwang-Ting Cheng

Keyword(s):

Test Generation ◽

Fault Testing ◽

Transition Fault ◽

Compact Test

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A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2016.20 ◽

2016 ◽

Cited By ~ 1

Author(s):

Irith Pomeranz

Keyword(s):

Test Generation ◽

Compact Set ◽

Test Set ◽

Compact Test

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Combined probabilistic testability calculation and compact test generation for PLAs

Journal of Electronic Testing ◽

10.1007/bf00135439 ◽

1991 ◽

Vol 2 (3) ◽

pp. 215-227 ◽

Cited By ~ 3

Author(s):

Bj�rg Reppen ◽

Einar J. Aas

Keyword(s):

Test Generation ◽

Compact Test

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Compact Test Generation for Small-Delay Defects Using Testable-Path Information

2009 Asian Test Symposium ◽

10.1109/ats.2009.44 ◽

2009 ◽

Author(s):

Dong Xiang ◽

Boxue Yin ◽

Krishendu Chakrabarty

Keyword(s):

Test Generation ◽

Small Delay Defects ◽

Path Information ◽

Small Delay ◽

Delay Defects ◽

Compact Test

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Compact test generation for full scan sequential circuits using multiple frame vectors

Electronics Letters ◽

10.1049/el:19990145 ◽

1999 ◽

Vol 35 (3) ◽

pp. 182

Author(s):

Dong Ho Lee ◽

Hyun Chul Noh

Keyword(s):

Test Generation ◽

Sequential Circuits ◽

Full Scan ◽

Multiple Frame ◽

Compact Test

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Test generation for digital circuits described by means of register transfer languages

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1987.0012 ◽

1987 ◽

Vol 134 (2) ◽

pp. 69 ◽

Cited By ~ 1

Author(s):

E. Villar ◽

S. Bracho

Keyword(s):

Test Generation ◽

Digital Circuits ◽

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Modelling Method of Web Navigation for Automatic Verification and Test Generation using State Machine Diagrams

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss.136.423 ◽

2016 ◽

Vol 136 (3) ◽

pp. 423-433

Author(s):

Tomoyuki Yokogawa ◽

Yoichiro Sato ◽

Kazutami Arimoto

Keyword(s):

Test Generation ◽

State Machine ◽

Automatic Verification ◽

Web Navigation ◽

Modelling Method

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Encoding Transparency: Literate Programming and Test Generation for Scientific Function Libraries

SSRN Electronic Journal ◽

10.2139/ssrn.2113535 ◽

2012 ◽

Author(s):

Mark D. Flood ◽

Matthew McCormick ◽

Nathan M. Palmer

Keyword(s):

Test Generation ◽

Literate Programming

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