scholarly journals Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models

2004 ◽  
Author(s):  
A. Krstic ◽  
L.-C. Wang ◽  
K.-T. Cheng ◽  
J.-J. Liou ◽  
T.M. Mak
Keyword(s):  
Fault Models ◽  
Statistical Timing ◽  
Delay Defects

A Case Study on the Benefits of Functional Memory Access during ATE Test and Electrical Fault Isolation Techniques for Embedded SRAM

2014 ◽  
Author(s):  
Corey Goodrich
Keyword(s):  
Fault Isolation ◽  
Test Coverage ◽  
Fault Models ◽  
Isolation Techniques ◽  
Diagnostic Capability ◽  
Delay Defects ◽  
Critical Paths ◽  
Scan Chain ◽  
Embedded Memories ◽  
Embedded Sram

Abstract Test coverage of embedded memories is often split between test modes. A BIST solution is typically used to isolate and test the memory array through test specific ports. The functional interconnect between logic and memory is tested with traditional ATPG test modes where a bypass cell on the scan chain is used to clock data through the memory. This approach may miss test coverage if the functional path is different from the test path[1]. Although commercial ATPG tools provide some capability in this area, the most advanced type of fault models which target small delay defects or cross talk faults are not as streamlined as they are for traditional fault models. Additionally, more advanced fault types don’t typically have the same diagnostic capability. In this paper, capabilities are developed for maximizing the effectiveness of test on embedded SRAM interconnects in an ATPG context. Also, a method is outlined to characterize and validate the timing robustness of the memory ports and provide a silicon diagnostic capability for localizing critical paths and isolating physical defects.

Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree

2011 ◽  
Author(s):  
Yu Huang ◽  
Wu-Tung Cheng ◽  
Ting-Pu Tai ◽  
Liyang Lai ◽  
Ruifeng Guo ◽  
...  
Keyword(s):  
Hold Time ◽  
Clock Signal ◽  
Clock Tree ◽  
Scan Testing ◽  
Design Error ◽  
Functional Logic ◽  
Scan Chains ◽  
Delay Defects

Abstract If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.

Logic Fault Diagnosis of Hidden Delay Defects

2020 ◽  
Author(s):  
Stefan Holst ◽  
Matthias Kampmann ◽  
Alexander Sprenger ◽  
Jan Dennis Reimer ◽  
Sybille Hellebrand ◽  
...  
Keyword(s):  
Fault Diagnosis ◽  
Delay Defects

Automatic Fault Tree Generation from Radiation-Induced Fault Models

2020 ◽  
Author(s):  
Rebekah A. Austin ◽  
Nagabhushan Mahadevan ◽  
Arthur F. Witulski ◽  
Gabor Karsai ◽  
Brian D. Sierawski ◽  
...  
Keyword(s):  
Fault Tree ◽  
Fault Models ◽  
Tree Generation ◽  
Radiation Induced

Fault models for the Bodrum–Kos tsunamigenic earthquake (Mw6.6) of 20 July 2017 in the east Aegean Sea

2019 ◽  
Vol 131 ◽  
pp. 101646 ◽  
Author(s):  
Gerassimos Papadopoulos ◽  
Apostolos Agalos ◽  
Marinos Charalampakis ◽  
Charalampos Kontoes ◽  
Ioannis Papoutsis ◽  
...  
Keyword(s):  
Aegean Sea ◽  
Fault Models ◽  
Tsunamigenic Earthquake
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