Transformation-based high-level synthesis of fault-tolerant ASICs

[1992] Proceedings 29th ACM/IEEE Design Automation Conference ◽

10.1109/dac.1992.227803 ◽

2003 ◽

Cited By ~ 24

Author(s):

R. Karri ◽

A. Orailoglu

Keyword(s):

Fault Tolerant ◽

High Level Synthesis ◽

High Level

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A high-level synthesis approach to design of fault-tolerant systems

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.600305 ◽

2002 ◽

Cited By ~ 6

Author(s):

G. Buonanno ◽

M. Pugassi ◽

M.G. Sami

Keyword(s):

Fault Tolerant ◽

High Level Synthesis ◽

Fault Tolerant Systems ◽

High Level ◽

Synthesis Approach

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A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2015.7245735 ◽

2015 ◽

Cited By ~ 4

Author(s):

Aniruddha Shastri ◽

Greg Stitt ◽

Eduardo Riccio

Keyword(s):

Fault Tolerant ◽

High Level Synthesis ◽

High Level

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A Design Methodology For The High-level Synthesis Of Fault-tolerant Asics

Workshop on VLSI Signal Processing ◽

10.1109/vlsisp.1992.641073 ◽

2005 ◽

Cited By ~ 13

Author(s):

A. Orailoglu ◽

R. Karri

Keyword(s):

Design Methodology ◽

Fault Tolerant ◽

High Level Synthesis ◽

High Level

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High-level synthesis of fault-tolerant ASICs

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.1992.229924 ◽

2003 ◽

Cited By ~ 8

Author(s):

R. Karri ◽

A. Orailoglu

Keyword(s):

Fault Tolerant ◽

High Level Synthesis ◽

High Level

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Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis

Expert Systems with Applications ◽

10.1016/j.eswa.2015.01.058 ◽

2015 ◽

Vol 42 (10) ◽

pp. 4719-4732 ◽

Cited By ~ 9

Author(s):

Anirban Sengupta ◽

Saumya Bhadauria

Keyword(s):

Fault Tolerant ◽

High Level Synthesis ◽

Power Performance ◽

Bacterial Foraging ◽

High Level ◽

Performance Tradeoff

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High-level synthesis for multi-cycle transient fault tolerant datapaths

2011 IEEE 17th International On-Line Testing Symposium ◽

10.1109/iolts.2011.5993804 ◽

2011 ◽

Cited By ~ 22

Author(s):

Tomoo Inoue ◽

Hayato Henmi ◽

Yuki Yoshikawa ◽

Hideyuki Ichihara

Keyword(s):

Fault Tolerant ◽

High Level Synthesis ◽

Transient Fault ◽

High Level

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

High Level ◽

Nested Loop

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

Ant Colony ◽

High Level Synthesis ◽

High Level

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