Real Time Cache Performance Analyzing for Multi-core Parallel Programs

2013 ◽  
Author(s):  
Rui Wang ◽  
Yuan Gao ◽  
Guolu Zhang
Keyword(s):  
Real Time ◽  
Parallel Programs ◽  
Cache Performance

Design of an Intelligent Data Cache with Replacement Policy

2019 ◽  
Vol 10 (2) ◽  
pp. 87-107
Author(s):  
B. Shameedha Begum ◽  
N. Ramasubramanian
Keyword(s):  
Real Time ◽  
Replacement Policy ◽  
Data Cache ◽  
Cache Performance ◽  
Performance Requirements ◽  
Novel Approach ◽  
Reconfigurable Caches ◽  
Real Time Applications ◽  
Hard Real Time ◽  
Replacement Algorithms

Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.

scholarly journals Answer Set versus Integer Linear Programming for Automatic Synthesis of Multiprocessor Systems from Real-Time Parallel Programs

2009 ◽  
Vol 2009 ◽  
pp. 1-11 ◽  
Author(s):  
Harold Ishebabi ◽  
Philipp Mahr ◽  
Christophe Bobda ◽  
Martin Gebser ◽  
Torsten Schaub
Keyword(s):  
Linear Programming ◽  
Real Time ◽  
Integer Linear Programming ◽  
Linear Equations ◽  
Parallel Programs ◽  
Design Parameters ◽  
Multiprocessor Systems ◽  
Task Mapping ◽  
Baseband Signal Processing ◽  
Answer Set

An automated design approach for multiprocessor systems on FPGAs is presented which customizes architectures for parallel programs by simultaneously solving the problems of task mapping, resource allocation, and scheduling. The latter considers effects of fixed-priority preemptive scheduling in order to guarantee real-time requirements, hence covering a broad spectrum of embedded applications. Being inherently a combinatorial optimization problem, the design space is modeled using linear equations that capture high-level design parameters. A comparison of two methods for solving resulting problem instances is then given. The intent is to study how well recent advances in propositional satisfiability (SAT) and thus Answer Set Programming (ASP) can be exploited to automate the design of flexible multiprocessor systems. Integer Linear Programming (ILP) is taken as a baseline, where architectures for IEEE 802.11g and WCDMA baseband signal processing are synthesized. ASP-based synthesis used a few seconds in the solver, faster by three orders of magnitude compared to ILP-based synthesis, thereby showing a great potential for solving difficult instances of the automated synthesis problem.

scholarly journals Automatic generation of scheduling and communication code in real-time parallel programs

1995 ◽  
Vol 30 (11) ◽  
pp. 134-145
Author(s):  
André Bakkers ◽  
Johan Sunter ◽  
Evert Ploeg
Keyword(s):  
Real Time ◽  
Automatic Generation ◽  
Parallel Programs

Design and Implementation of Task Reprocessing on Medium-large Multi-core Architecture

2017 ◽  
Vol 2 (3) ◽  
pp. 25 ◽  
Author(s):  
PAVAN KUMAR PARUCHURI ◽  
Satyanarayana CH ◽  
Ananda Rao A ◽  
Radica Raju P
Keyword(s):  
Real Time ◽  
Cache Performance ◽  
Average Case ◽  
Real Time Scheduling ◽  
Shared Cache ◽  
Time Scheduling ◽  
Hard Real Time ◽  
Exploratory Procedure ◽  
Task Sets ◽  
Time Systems

EDF-Based real-time scheduling approach is one of the efficient way of scheduling the recurrent real-time tasks in both soft real-time and hard real-time systems. EDF algorithms entile heavy overhead due to lower scheduling and huge migration. In this paper, an exploratory procedure has been presented for reprocessing of neglected task sets and also examine, whether an improved heuristic set attributed as Enhanced shared CAche Performance (ENCAP) can improve the shared cache performance which processes the task set based on Earliest-Deadline-First (EDF). An Object-Oriented real-time code reusable scheduling components which is designed from the scratch referred as LITMUSRT has been used to test the efficiency and average-case accomplishments where per task utilizations are shortened and overall utilization are not restricted. We also discuss the implementation and experimental evaluation of Task-Repo procedure for co-scheduling task sets, under the utilization of 50-60% (per-task) on small to medium-large multicore LINUX SYSTEM.

Sign in / Sign up

Export Citation Format

Share Document