An approach to exploiting proper multiples of the generator polynomial in parallel CRC computation

2012 ◽  
Author(s):  
MohammadReza Mehrabian ◽  
Saadat Pour Mozafari ◽  
Behrouz Zolfaghari
Keyword(s):  
Generator Polynomial

Low complexity bit-parallel multipliers for GF(2m) with generator polynomial xm + xk + 1

1999 ◽  
Vol 35 (7) ◽  
pp. 551 ◽  
Author(s):  
M. Elia ◽  
M. Leone ◽  
C. Visentin
Keyword(s):  
Low Complexity ◽  
Generator Polynomial

scholarly journals Generalizing Krawtchouk Polynomials Using Hadamard Matrices

2014 ◽  
Vol 2014 ◽  
pp. 1-8
Author(s):  
Peter S. Chami ◽  
Bernd Sing ◽  
Norris Sookoo
Keyword(s):  
Recurrence Relations ◽  
Hadamard Matrix ◽  
Hadamard Matrices ◽  
Krawtchouk Polynomials ◽  
Generator Polynomial ◽  
Orthogonality Relations ◽  
Square Matrix

We investigate polynomials, called m-polynomials, whose generator polynomial has coefficients that can be arranged in a square matrix; in particular, the case where this matrix is a Hadamard matrix is considered. Orthogonality relations and recurrence relations are established, and coefficients for the expansion of any polynomial in terms of m-polynomials are obtained. We conclude this paper by an implementation of m-polynomials and some of the results obtained for them in Mathematica.

High speed CRC with 64-bit generator polynomial on an FPGA

2011 ◽  
Vol 39 (4) ◽  
pp. 72-77 ◽  
Author(s):  
Amila Akagić ◽  
Hideharu Amano
Keyword(s):  
High Speed ◽  
Generator Polynomial

scholarly journals XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware

2016 ◽  
Vol 2016 ◽  
pp. 1-8 ◽  
Author(s):  
Gaurav Purohit ◽  
Kota Solomon Raju ◽  
Vinod Kumar Chaubey
Keyword(s):  
Propagation Delay ◽  
Code Rate ◽  
Reconfigurable Hardware ◽  
Lookup Table ◽  
Hardware Cost ◽  
Matlab Simulink ◽  
Generator Polynomial ◽  
Dynamic Power ◽  
Constraint Length ◽  
Convolutional Encoder

This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW) implementation of new architecture uses Lookup Table (LUT) for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.

Decoding Reed-Solomon codes generated by any generator polynomial

1989 ◽  
Vol 25 (18) ◽  
pp. 1223 ◽  
Author(s):  
Y.R. Shayan ◽  
T. Le-Ngoc
Keyword(s):  
Generator Polynomial ◽  
Reed Solomon Codes
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