Analysis and comparative evaluation of stacked-transistor half-bridge topologies implemented with 14 nm bulk CMOS technology
1986 ◽
Vol 51
(4)
◽
pp. 362-369
◽
Keyword(s):
Keyword(s):
1988 ◽
Vol 49
(C4)
◽
pp. C4-421-C4-424
◽