Analyzing performance of joint SVR interpolation for LTE system with 64-QAM modulation under 500 Km/h mobile velocity

Author(s):  
Anis Charrada ◽  
Abdelaziz Samet
Keyword(s):  
2020 ◽  
Vol 0 (0) ◽  
Author(s):  
Hocine Fekih ◽  
Boubakar Seddik Bouazza ◽  
Keltoum Nouri

AbstractRecently, using iterative decoding algorithms to achieve an interesting bit error rate for spectrally efficient modulation become a necessity for optical transmission, in this paper, we propose a coded modulation scheme based on bit interleaving circular recursive systematic convolutional (CRSC) code and 16-QAM modulation. The proposal system considered as a serial concatenation of a channel encoder, a bit interleaver and M-ary modulator can be flexible easy to implement using a short code length. For a spectral efficiency $\eta =3\text{bit}/s/Hz$, the coding gain at a bit error rate of 10−6 is about 8 dB.


2019 ◽  
Vol 37 (3) ◽  
pp. 815-823 ◽  
Author(s):  
Amin Yekani ◽  
Leslie A. Rusch

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Panagiotis K. Gkonis ◽  
Maria A. Seimeni ◽  
Nikolaos P. Asimakis ◽  
Dimitra I. Kaklamani ◽  
Iakovos S. Venieris

The goal of the study presented in this paper is to investigate the performance of a new subcarrier allocation strategy for Orthogonal Frequency Division Multiple Access (OFDMA) multicellular networks which employ Multiple Input Multiple Output (MIMO) architecture. For this reason, a hybrid system-link level simulator has been developed executing independent Monte Carlo (MC) simulations in parallel. Up to two tiers of cells around the central cell are taken into consideration and increased loading per cell. The derived results indicate that this strategy can provide up to 12% capacity gain for 16-QAM modulation and two tiers of cells around the central cell in a symmetric2×2MIMO configuration. This gain is derived when comparing the proposed strategy to the traditional approach of allocating subcarriers that maximize only the desired user’s signal.


Author(s):  
Sarah Zanafi ◽  
Noura Aknin

<span>In this work, the influence of the cyclic prefix on the performance of the OFDM system is studied. We worked out an OFDM transceiver using a 16 QAM modulation scheme, a comparison of the BER for various lengths of the cyclic prefix has been achieved, and the influence of the noise introduced in the channel has been highlighted, for both a Gaussian and Rayleigh noise. The simulation was carried out on MATLAB where the curves of the BER for various lengths of the cyclic prefix are given and compared. We also adopted as a metric the QAM constellation to show the dispersion of the carriers as a consequence of the transmission channel, the mitigation of this effect by the CP is noticeable.</span>


2015 ◽  
Vol 13 ◽  
pp. 73-80 ◽  
Author(s):  
I. Ali ◽  
U. Wasenmüller ◽  
N. Wehn

Abstract. Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.


2009 ◽  
Vol 27 (18) ◽  
pp. 4105-4111 ◽  
Author(s):  
Kyoungsoo Kim ◽  
Jaehoon Lee ◽  
Jichai Jeong

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