scholarly journals A Low-Complexity Graph-Based LMMSE Receiver for MIMO ISI Channels With $M$ -QAM Modulation

2017 ◽  
Vol 16 (2) ◽  
pp. 1185-1195 ◽  
Author(s):  
Pinar Sen ◽  
Ali Ozgur Yilmaz
Keyword(s):  
Low Complexity ◽  
Qam Modulation ◽  
Isi Channels

scholarly journals A high throughput architecture for a low complexity soft-output demapping algorithm

2015 ◽  
Vol 13 ◽  
pp. 73-80 ◽  
Author(s):  
I. Ali ◽  
U. Wasenmüller ◽  
N. Wehn
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Turbo Code ◽  
Low Complexity ◽  
Implementation Cost ◽  
Qam Modulation ◽  
Iterative Systems ◽  
Very High ◽  
Complexity Algorithm ◽  
Hardware Performance

Abstract. Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.

scholarly journals Low-Complexity Iterative Detection in Multi-User MIMO ISI Channels

2008 ◽  
Vol 15 ◽  
pp. 25-28 ◽  
Author(s):  
Xiaojun Yuan ◽  
Qinghua Guo ◽  
Li Ping
Keyword(s):  
Low Complexity ◽  
Iterative Detection ◽  
Isi Channels

scholarly journals Low-complexity carrier phase recovery based on principal component analysis for square-QAM modulation formats

2019 ◽  
Vol 27 (11) ◽  
pp. 15617 ◽  
Author(s):  
Júlio César Medeiros Diniz ◽  
Qirui Fan ◽  
Stenio Magalhães Ranzini ◽  
Faisal Nadeem Khan ◽  
Francesco Da Ros ◽  
...  
Keyword(s):  
Principal Component Analysis ◽  
Carrier Phase ◽  
Principal Component ◽  
Low Complexity ◽  
Component Analysis ◽  
Modulation Formats ◽  
Phase Recovery ◽  
Qam Modulation

scholarly journals Low-Complexity Detection in Large-Dimension MIMO-ISI Channels Using Graphical Models

2011 ◽  
Vol 5 (8) ◽  
pp. 1497-1511 ◽  
Author(s):  
Pritam Som ◽  
Tanumay Datta ◽  
N. Srinidhi ◽  
A. Chockalingam ◽  
B. Sundar Rajan
Keyword(s):  
Graphical Models ◽  
Low Complexity ◽  
Large Dimension ◽  
Isi Channels
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