Enhanced Throughput and Energy-Efficient MRAM-Based NB-LDPC Decoder

This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.

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Asynchronous design for precision-scaleable energy-efficient LDPC decoder

2014 48th Asilomar Conference on Signals, Systems and Computers ◽

10.1109/acssc.2014.7094413 ◽

2014 ◽

Author(s):

Jingwei Xu ◽

Tiben Che ◽

Ehsan Rohani ◽

Gwan Choi

Keyword(s):

Energy Efficient ◽

Asynchronous Design ◽

Ldpc Decoder

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An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard

SiPS 2013 Proceedings ◽

10.1109/sips.2013.6674490 ◽

2013 ◽

Cited By ~ 9

Author(s):

Meng Li ◽

Frederik Naessens ◽

Peter Debacker ◽

Praveen Raghavan ◽

Claude Desset ◽

...

Keyword(s):

Energy Efficient ◽

Ldpc Decoder

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High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401163 ◽

2021 ◽

Author(s):

Chao Zhang ◽

Jingtong Mo ◽

Zihan Lian ◽

Weifeng He

Keyword(s):

Flash Memory ◽

Energy Efficient ◽

High Energy ◽

Nand Flash ◽

Nand Flash Memory ◽

Ldpc Decoder

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LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

VLSI Design ◽

10.1155/2013/913018 ◽

2013 ◽

Vol 2013 ◽

pp. 1-14 ◽

Cited By ~ 4

Author(s):

Tinoosh Mohsenin ◽

Houshmand Shirani-mehr ◽

Bevan M. Baas

Keyword(s):

Low Power ◽

Energy Efficient ◽

State Of The Art ◽

Average Power ◽

Parity Check ◽

Ldpc Decoder ◽

Low Density Parity Check ◽

Variable Node ◽

Power Mode ◽

Ber Performance

An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65 nm CMOS. A 5.10 mm2 low power decoder implementation achieves 85.7 Gbps while operating at 185 MHz and dissipates 16.4 pJ/bit at 1.3 V with early termination. At 0.6 V the decoder throughput is 9.3 Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31 mW. This is 4.6 lower than the state of the art reported power with an SNR loss of 0.35 dB at .

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