Low loss and high isolation Ka-band SPDT switch

2012 ◽  
Author(s):  
G. A. Kumar ◽  
Arun Kumar
Keyword(s):  
Low Loss ◽  
Ka Band ◽  
High Isolation

A novel Ka-band MMIC coupled filter with harmonic suppression

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 169-173
Author(s):  
Jin Guan ◽  
Min Gong ◽  
Bo Gao
Keyword(s):  
Pass Band ◽  
Wave System ◽  
Harmonic Suppression ◽  
Low Loss ◽  
Coupled Line ◽  
Ka Band ◽  
Content Type ◽  
Harmonic Frequencies ◽  
Full Wave ◽  
On Chip

Purpose A novel Ka-band compact parallel-coupled microstrip bandpass filter with harmonic suppression performance has been designed, implemented and tested on GaAs MMIC. Design/methodology/approach This proposed filter consists of modified coupled-line units with T-shaped open-stubs. Findings The proposed filter with T-shaped open-stubs is valuable in performance with low loss at fundamental frequency, suppression at harmonic frequencies and small size. The simulation is based on full-wave electromagnetic analysis and the measurement is based on chip test. It shows an insertion loss below 1.2 dB, return loss better than 20 dB in the pass band and high than 28 dB suppression at harmonic frequencies. Originality/value This Ka-band MMIC filter with harmonic suppression is attractive for the millimeter-wave system.

A Low-Loss and High-Isolation Transformer-Based mm-Wave SPDT with Integrated Fan-out Wafer Level Packaging

2019 ◽  
Vol 29 (07) ◽  
pp. 2050115
Author(s):  
Xing Quan ◽  
Jiang Luo ◽  
Guodong Su ◽  
Kai Jing ◽  
Jinsong Zhan
Keyword(s):  
Design Method ◽  
Control Device ◽  
Secondary Coil ◽  
Cmos Process ◽  
Wafer Level ◽  
Low Loss ◽  
High Isolation ◽  
Wafer Level Packaging ◽  
Isolation Transformer ◽  
Better Than

This paper proposes a low-loss and high-isolation transformer (TF)-based mm-wave single-pole double-throw (SPDT) switch. The center-tapped technique is employed at the secondary coil of TF to improve isolation performance. The TF is implemented with the metals in redistribution layers (RDLs) in integrated fan-out (InFO) wafer level packaging technology to obtain low insertion loss (IL) and small chip size as the TF usually dominates the area of SPDT. The control device of the SPDT is realized in 40[Formula: see text]nm bulk CMOS process. The simulated result shows the proposed SPDT achieves a minimum IL of 1.34[Formula: see text]dB and the IL is less than 2.2[Formula: see text]dB at 24–31[Formula: see text]GHz. The isolations are better than 27[Formula: see text]dB between two double-throw ports and better than 20[Formula: see text]dB between single-pole and double-throw ports, respectively. The proposed SPDT has a compact silicon size of 220[Formula: see text][Formula: see text] (with PADs) and its return losses are better than [Formula: see text]9[Formula: see text]dB at 24–31[Formula: see text]GHz and. This work explores a new chip-package co-design method for the SPDT and may have some guidance for the co-design of SPDT and antenna in package (AiP).

Low-loss Ka-band frequency selective subreflector

1991 ◽  
Vol 27 (13) ◽  
pp. 1155 ◽  
Author(s):  
K. Ueno ◽  
H. Kumazawa ◽  
I. Ohtomo
Keyword(s):  
Low Loss ◽  
Band Frequency ◽  
Ka Band ◽  
Frequency Selective
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