PAFBV: A Novel Parallel Aggregated and Folded Bit Vector Packet Classification Scheme for IPv6 Routers

2006 ◽  
Author(s):  
A. Azeezunnisa ◽  
T Srinivasan ◽  
D. Vijayalakshmi
Keyword(s):  
Classification Scheme ◽  
Packet Classification ◽  
Bit Vector

scholarly journals Memory Optimization for Bit-Vector-Based Packet Classification on FPGA

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1159 ◽  
Author(s):  
Chenglong Li ◽  
Tao Li ◽  
Junnan Li ◽  
Dagang Li ◽  
Hui Yang ◽  
...  
Keyword(s):  
High Throughput ◽  
High Performance ◽  
Classification Scheme ◽  
Packet Classification ◽  
Memory Consumption ◽  
The Past ◽  
Large Memory ◽  
Bit Vector ◽  
Memory Resources ◽  
Very High

High-performance packet classification algorithms have been widely studied during the past decade. Bit-Vector-based algorithms proposed for FPGA can achieve very high throughput by decomposing rules delicately. However, the relatively large memory resources consumption severely hinders applications of the algorithms extensively. It is noteworthy that, in the Bit-Vector-based algorithms, stringent memory resources in FPGA are wasted to store relatively plenty of useless wildcards in the rules. We thus present a memory-optimized packet classification scheme named WeeBV to eliminate the memory occupied by the wildcards. WeeBV consists of a heterogeneous two-dimensional lookup pipeline and an optimized heuristic algorithm for searching all the wildcard positions that can be removed. It can achieve a significant reduction in memory resources without compromising the high throughput of the original Bit-Vector-based algorithms. We implement WeeBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can save 37% and 41% memory consumption on average for synthetic 5-tuple rules and OpenFlow rules respectively.

New Fields in Classifying Algorithms for Content Awareness

2012 ◽  
Vol 7 (2) ◽  
pp. 1-15
Author(s):  
Radu-Dinel Miruta ◽  
Cosmin Stanuica ◽  
Eugen Borcoci
Keyword(s):  
Packet Classification ◽  
Tuple Space ◽  
New Approach ◽  
Data Packets ◽  
Server Side ◽  
The Media ◽  
Bit Vector ◽  
Edge Router ◽  
Content Aware

The content aware (CA) packet classification and processing at network level is a new approach leading to significant increase of delivery quality of the multimedia traffic in Internet. This paper presents a solution for a new multi-dimensional packet classifier of an edge router, based on content - related new fields embedded in the data packets. The technique is applicable to content aware networks. The classification algorithm is using three new packet fields named Virtual Content Aware Network (VCAN), Service Type (STYPE), and U (unicast/multicast) which are part of the Content Awareness Transport Information (CATI) header. A CATI header is inserted into the transmitted data packets at the Service/Content Provider server side, in accordance with the media service definition, and enables the content awareness features at a new overlay Content Aware Network layer. The functionality of the CATI header within the classification process is then analyzed. Two possibilities are considered: the adaptation of the Lucent Bit vector algorithm and, respectively, of the tuple space search, in order to respond to the suggested multi-fields classifier. The results are very promising and they prove that theoretical model of inserting new packet fields for content aware classification can be implemented and can work in a real time classifier.

scholarly journals Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA

2020 ◽  
Vol 12 (8) ◽  
pp. 3068 ◽  
Author(s):  
Chenglong Li ◽  
Tao Li ◽  
Junnan Li ◽  
Zilin Shi ◽  
Baosheng Wang
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Recursive Algorithm ◽  
Packet Classification ◽  
Experimental Results ◽  
The Core ◽  
Core Function ◽  
Field Programmable ◽  
Bit Vector

Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.

scholarly journals Design of a Low Latency and High Throughput Packet Classification Module on FPGA Platform

2020 ◽  
Vol 9 (4) ◽  
pp. 1468-1474
Keyword(s):  
High Speed ◽  
Network Performance ◽  
Packet Classification ◽  
Total Power ◽  
Network Systems ◽  
Chip Area ◽  
Packet Header ◽  
Rule Set ◽  
Bit Vector ◽  
Ip Packet

The Packet classification method plays a significant role in most of the Network systems. These systems categories the incoming packets in various flows and takes suitable action based on the requirements. If the size of the network is vast and complexity will arise to perform the different operations, which affects the network performance and other constraints also. So there is the demand for high-speed packet classifiers to reduce the network complexity and improve the network performance. In this article, The Bit vector Packet classifier (BV-PC) Module is designed to improve the network system performance and overcome the existing limitation of Packet classification approaches on FPGA. The BV-PC Module contains Packet generation Unit (PGU) to receive the valid incoming packets, Memory Unit (MU) to store valid packets, Header Extractor Unit (HEU) extracts the IP Header address information from the Valid packets, The BV-Based Source and Destination Address (BV-SA, BV-DA) unit receives the IP packet header Information and Process with BV based rule set and aggregates the BV-SA and BV-DA outputs, Priority Encoder encodes the Highest priority BV Rule for the generation of Classified output. The BV-PC utilizes <2% Chip area (slices), works at 509.38MHz, and consumed Less 0.103 W of total Power on Artix-7 FPGA. The BV-PC operates with a latency of 5 clock cycles and works at 815.03Mpps throughput. The BV-PC is compared with existing approaches and provides Better improvements in Hardware constraints.

scholarly journals Enhancing the performance of the aggregated bit vector algorithm in network packet classification using GPU

2019 ◽  
Vol 5 ◽  
pp. e185 ◽  
Author(s):  
Mahdi Abbasi ◽  
Razieh Tahouri ◽  
Milad Rafiee
Keyword(s):  
Graphics Processing Units ◽  
High Speed ◽  
Parallel Implementation ◽  
Packet Classification ◽  
Experimental Results ◽  
Analysis Method ◽  
Network Systems ◽  
Computationally Intensive ◽  
Bit Vector ◽  
Graphics Processing

Packet classification is a computationally intensive, highly parallelizable task in many advanced network systems like high-speed routers and firewalls that enable different functionalities through discriminating incoming traffic. Recently, graphics processing units (GPUs) have been exploited as efficient accelerators for parallel implementation of software classifiers. The aggregated bit vector is a highly parallelizable packet classification algorithm. In this work, first we present a parallel kernel for running this algorithm on GPUs. Next, we adapt an asymptotic analysis method which predicts any empirical result of the proposed kernel. Experimental results not only confirm the efficiency of the proposed parallel kernel but also reveal the accuracy of the analysis method in predicting important trends in experimental results.

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