A Low-Power Efficient Direct Digital Frequency Synthesizer Based on New Two-Level Lookup Table

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

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An area efficient memory-less ROM design architecture for direct digital frequency synthesizer

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v11i1.pp257-264 ◽

2021 ◽

Vol 11 (1) ◽

pp. 257

Author(s):

Salah Alkurwy ◽

Sawal H. Ali ◽

Md. Shabiul Islam ◽

Faizul Idros

Keyword(s):

Frequency Synthesizer ◽

Logic Gate ◽

Lookup Table ◽

Verilog Hdl ◽

Digital Frequency ◽

Novel Approach ◽

Direct Digital Frequency Synthesizer ◽

A New Technique ◽

Simple Logic ◽

Efficient Memory

This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

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Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

IEEE Access ◽

10.1109/access.2020.2986016 ◽

2020 ◽

Vol 8 ◽

pp. 67581-67590

Author(s):

Ji-Min Choi ◽

Dong-Hyun Yoon ◽

Dong-Kyu Jung ◽

Kiho Seong ◽

Jae-Soub Han ◽

...

Keyword(s):

Low Power ◽

Frequency Synthesizer ◽

Digital Frequency ◽

Direct Digital Frequency Synthesizer

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