Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units

2014 IEEE 23rd Asian Test Symposium ◽

10.1109/ats.2014.61 ◽

2014 ◽

Cited By ~ 3

Author(s):

Yussuf Ali ◽

Yuta Yamato ◽

Tomokazu Yoneda ◽

Kazumi Hatayama ◽

Michiko Inoue

Keyword(s):

Fault Simulation ◽

Path Delay ◽

Delay Fault ◽

Parallel Path ◽

Path Delay Fault ◽

Many Core

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Path delay fault simulation algorithms for sequential circuits

Proceedings First Asian Test Symposium (ATS `92) ◽

10.1109/ats.1992.224444 ◽

2003 ◽

Cited By ~ 13

Author(s):

T.J. Chakraborty ◽

V.D. Agrawal ◽

M.L. Bushnell

Keyword(s):

Fault Simulation ◽

Sequential Circuits ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Simulation Algorithms

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Parallel concurrent path-delay fault simulation using single-input change patterns

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489647 ◽

2002 ◽

Cited By ~ 4

Author(s):

M.A. Gharaybeh ◽

M.L. Bushnell ◽

V.D. Agrawal

Keyword(s):

Fault Simulation ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Single Input

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Accelerated path delay fault simulation

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232715 ◽

2003 ◽

Author(s):

Yuejian Wu ◽

A. Ivanov

Keyword(s):

Fault Simulation ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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On Accelerating Path Delay Fault Simulation of Long Test Sequences

2008 IEEE International Test Conference ◽

10.1109/test.2008.4700625 ◽

2008 ◽

Author(s):

I-De Huang ◽

Yi-Shing Chang ◽

S. Natarajan ◽

R. Sharma ◽

S.K. Gupta

Keyword(s):

Fault Simulation ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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Path delay fault simulation of sequential circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.831443 ◽

2000 ◽

Vol 8 (2) ◽

pp. 223-228 ◽

Cited By ~ 7

Author(s):

T.J. Chakraborty ◽

V.D. Agrawal ◽

M.L. Bushnell

Keyword(s):

Fault Simulation ◽

Sequential Circuits ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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Path Delay Fault Simulation on Large Industrial Designs

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.55 ◽

2006 ◽

Cited By ~ 8

Author(s):

S. Natarajan ◽

S. Patil ◽

S. Chakravarty

Keyword(s):

Fault Simulation ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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FSimGEO: a test generation method for path delay fault test using fault simulation and genetic optimization

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558) ◽

10.1109/asic.2001.954702 ◽

2002 ◽

Author(s):

Sun Yihe ◽

Wu Qifa

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Genetic Optimization ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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Efficient path-delay fault simulation for standard scan design

IEE Proceedings - Circuits Devices and Systems ◽

10.1049/ip-cds:20020496 ◽

2002 ◽

Vol 149 (5) ◽

pp. 315-320

Author(s):

S. Kang

Keyword(s):

Fault Simulation ◽

Path Delay ◽

Scan Design ◽

Delay Fault ◽

Path Delay Fault

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Robust and nonrobust path delay fault simulation by parallel processing of patterns

IEEE Transactions on Computers ◽

10.1109/12.214661 ◽

1992 ◽

Vol 41 (12) ◽

pp. 1527-1536 ◽

Cited By ~ 12

Author(s):

F. Fink ◽

K. Fuchs ◽

M.H. Schulz

Keyword(s):

Parallel Processing ◽

Fault Simulation ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault

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Path-delay fault simulation for a standard scan design methodology

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1994.331926 ◽

2002 ◽

Author(s):

Sungho Kang ◽

Wai-On Law ◽

B. Underwood

Keyword(s):

Design Methodology ◽

Fault Simulation ◽

Path Delay ◽

Scan Design ◽

Delay Fault ◽

Path Delay Fault

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