A Scan Chain Adjustment Technology for Test Power Reduction

Author(s):  
Jia LI ◽  
Yu HU ◽  
Xiaowei LI
Author(s):  
Melanie Elm ◽  
Hans-Joachim Wunderlich ◽  
Michael E. Imhof ◽  
Christian G. Zoellin ◽  
Jens Leenstra ◽  
...  

2020 ◽  
Vol 67 (12) ◽  
pp. 3432-3436
Author(s):  
Sangjun Lee ◽  
Kyunghwan Cho ◽  
Sungki Choi ◽  
Sungho Kang

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6111
Author(s):  
Sangjun Lee ◽  
Kyunghwan Cho ◽  
Jihye Kim ◽  
Jongho Park ◽  
Inhwan Lee ◽  
...  

Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.


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