Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression

2005 ◽  
Author(s):  
H. Nakamura ◽  
A. Shirokane ◽  
Y. Nishizaki ◽  
A. Uzzaman ◽  
V. Chickermane ◽  
...  
Keyword(s):  
Low Cost ◽  
Delay Testing ◽  
Test Compression ◽  
On Chip

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

scholarly journals Design and Manufacturing of a Disposable, Cyclo-Olefin Copolymer, Microfluidic Device for a Biosensor †

Sensors ◽  
2019 ◽  
Vol 19 (5) ◽  
pp. 1178 ◽  
Author(s):  
Jorge Prada ◽  
Christina Cordes ◽  
Carsten Harms ◽  
Walter Lang
Keyword(s):  
Microfluidic Device ◽  
Heating Temperature ◽  
Low Cost ◽  
Reaction Chamber ◽  
Microfluidic System ◽  
Heating Process ◽  
Design And Manufacturing ◽  
On Chip ◽  
Working Parameters ◽  
Auto Fluorescence

This contribution outlines the design and manufacturing of a microfluidic device implemented as a biosensor for retrieval and detection of bacteria RNA. The device is fully made of Cyclo-Olefin Copolymer (COC), which features low auto-fluorescence, biocompatibility and manufacturability by hot-embossing. The RNA retrieval was carried on after bacteria heat-lysis by an on-chip micro-heater, whose function was characterized at different working parameters. Carbon resistive temperature sensors were tested, characterized and printed on the biochip sealing film to monitor the heating process. Off-chip and on-chip processed RNA were hybridized with capture probes on the reaction chamber surface and identification was achieved by detection of fluorescence tags. The application of the mentioned techniques and materials proved to allow the development of low-cost, disposable albeit multi-functional microfluidic system, performing heating, temperature sensing and chemical reaction processes in the same device. By proving its effectiveness, this device contributes a reference to show the integration potential of fully thermoplastic devices in biosensor systems.

On-Chip Fabrication of None-Dead-Volume Microtips for ESI-MS Applications

2007 ◽  
Vol 121-123 ◽  
pp. 611-614
Author(s):  
Che Hsin Lin ◽  
Jen Taie Shiea ◽  
Yen Lieng Lin
Keyword(s):  
Surface Tension ◽  
Low Cost ◽  
Microfluidic Channel ◽  
Dead Volume ◽  
Esi Ms ◽  
Rapid Fabrication ◽  
Chip Fabrication ◽  
Novel Method ◽  
On Chip ◽  
Highly Uniform

This paper proposes a novel method to on-chip fabricate a none-dead-volume microtip for ESI-MS applications. The microfluidic chip and ESI tip are fabricated in low-cost plastic based materials using a simple and rapid fabrication process. A constant-speed-pulling method is developed to fabricate the ESI tip by pulling mixed PMMA glue using a 30-μm stainless wire through the pre-formed microfluidic channel. The equilibrium of surface tension of PMMA glue will result in a sharp tip after curing. A highly uniform micro-tip can be formed directly at the outlet of the microfluidic channel with minimum dead-volume zone. Detection of caffeine, myoglobin, lysozyme and cytochrome C biosamples confirms the microchip device can be used for high resolution ESI-MS applications.

Optical MEMS platform for low-cost on-chip integration of planar light circuits and optical switching

2004 ◽  
Author(s):  
Kristine A. German ◽  
Joel Kubby ◽  
Jingkuang Chen ◽  
James Diehl ◽  
Kathleen Feinberg ◽  
...  
Keyword(s):  
Optical Switching ◽  
Low Cost ◽  
Optical Mems ◽  
On Chip

scholarly journals The Rise of the OM-LoC: Opto-Microfluidic Enabled Lab-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1467
Author(s):  
Harry Dawson ◽  
Jinane Elias ◽  
Pascal Etienne ◽  
Sylvie Calas-Etienne
Keyword(s):  
Low Cost ◽  
Optical Components ◽  
New Era ◽  
Lab On Chip ◽  
Highly Sensitive ◽  
Multiple Challenges ◽  
On Chip ◽  
Optical Circuits ◽  
Made In

The integration of optical circuits with microfluidic lab-on-chip (LoC) devices has resulted in a new era of potential in terms of both sample manipulation and detection at the micro-scale. On-chip optical components increase both control and analytical capabilities while reducing reliance on expensive laboratory photonic equipment that has limited microfluidic development. Notably, in-situ LoC devices for bio-chemical applications such as diagnostics and environmental monitoring could provide great value as low-cost, portable and highly sensitive systems. Multiple challenges remain however due to the complexity involved with combining photonics with micro-fabricated systems. Here, we aim to highlight the progress that optical on-chip systems have made in recent years regarding the main LoC applications: (1) sample manipulation and (2) detection. At the same time, we aim to address the constraints that limit industrial scaling of this technology. Through evaluating various fabrication methods, material choices and novel approaches of optic and fluidic integration, we aim to illustrate how optic-enabled LoC approaches are providing new possibilities for both sample analysis and manipulation.

Low cost optical particle detection for lab on chip systems based on DVD technology

2007 ◽  
Author(s):  
Andrew L. Clow ◽  
Rainer Künnemeyer ◽  
Paul Gaynor ◽  
John C. Sharpe
Keyword(s):  
Low Cost ◽  
Particle Detection ◽  
Lab On Chip ◽  
On Chip

On-chip spectrometer for low-cost optical coherence tomography

2014 ◽  
Author(s):  
Arthur Nitkowski ◽  
Kyle Preston ◽  
Nicolás Sherwood-Droz ◽  
Bradley S. Schmidt ◽  
Arsen R. Hajian
Keyword(s):  
Optical Coherence Tomography ◽  
Low Cost ◽  
Optical Coherence ◽  
On Chip

Smartphone integrated optoelectrowetting (SiOEW) for on-chip sample processing and microscopic detection of water quality

Lab on a Chip ◽  
2018 ◽  
Vol 18 (3) ◽  
pp. 532-539 ◽  
Author(s):  
Dongyue Jiang ◽  
Seunguk Lee ◽  
Sung Woo Bae ◽  
Sung-Yong Park
Keyword(s):  
Water Quality ◽  
Sample Preparation ◽  
Low Cost ◽  
Sample Processing ◽  
Microscopic Detection ◽  
Chip Sample ◽  
On Chip

We present a smartphone integrated optoelectrowetting (SiOEW) device as a low-cost, portable tool for on-chip sample preparation and microscopic detection of water quality.

Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001486-001519
Author(s):  
Curtis Zwenger ◽  
JinYoung Khim ◽  
YoonJoo Khim ◽  
SeWoong Cha ◽  
SeungJae Lee ◽  
...  
Keyword(s):  
Low Cost ◽  
Ease Of Use ◽  
Wafer Level ◽  
3D Structures ◽  
Wafer Level Packaging ◽  
Functional Convergence ◽  
3D Packaging ◽  
Improved Design ◽  
On Chip ◽  
Mobile Handset

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules to be applied compared to competing laminate-based technologies. In addition, the unique characteristics of WLFO enable innovative 3D structures to be created that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of WLFO and its extension into unique 3D structures. In addition, the advantages of these WLFO designs will be reviewed in comparison to current competing packaging technologies. Process & material characterization, design simulation, and reliability data will be presented to show how WLFO is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.

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