Verification of delayed-reset domino circuits using ATACS

2003 ◽  
Author(s):  
W. Belluomini ◽  
C.J. Myers ◽  
H.P. Hofstee
Keyword(s):  
Domino Circuits

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

FDSTDL: Low‐power technique for FinFET domino circuits

2019 ◽  
Vol 47 (6) ◽  
pp. 917-940 ◽  
Author(s):  
Sandeep Garg ◽  
Tarun K. Gupta
Keyword(s):  
Low Power ◽  
Domino Circuits

Performance Analysis of Dual Vt Domino Circuits with P-V-T Variations

2011 ◽  
Vol 88-89 ◽  
pp. 326-330 ◽  
Author(s):  
Jin Hui Wang ◽  
Na Gong ◽  
Gang Liu ◽  
Shu Qin Geng ◽  
Wu Chen Wu
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Method ◽  
Performance Analysis ◽  
Leakage Current ◽  
Active Power ◽  
Performance Estimation ◽  
Temperature Variations ◽  
Multiple Parameter ◽  
Domino Circuits ◽  
Level Performance

The leakage current, active power and delay characterizations of the domino circuits in the presence of P-V-T (Process, Voltage, and Temperature) variations are analyzed based on multiple-parameter Monte Carlo method. It is demonstrated that failing to account for P-V-T variations and process-electro-thermal couplings can result in significant inaccuracy in transistor-level performance estimation. It also indicates that under significant P-V-T variations, DTV (Dual VtTechnology) is still highly effective to reduce the leakage current and active power for domino circuits, but induces speed penalty. At last, the robustness of different domino circuits with DTV against the P-V-T variations is discussed.

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