FDSTDL: Low‐power technique for FinFET domino circuits

2019 ◽  
Vol 47 (6) ◽  
pp. 917-940 ◽  
Author(s):  
Sandeep Garg ◽  
Tarun K. Gupta
Keyword(s):  
Low Power ◽  
Domino Circuits

A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-in OR Logic

2021 ◽  
pp. 2250055
Author(s):  
Ankur Kumar ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Noise Immunity ◽  
Cmos Technology ◽  
Threshold Current ◽  
Delay Condition ◽  
Noise Margin ◽  
Novel Method ◽  
Domino Circuits

This paper proposes a novel method to control leakage and noise in domino circuits for wide fan-in OR logic with low power consumption, low process variation, and higher noise margin under the similar delay condition. In the proposed method, output and dynamic nodes are isolated from the PDN (Pull-Down Network) to improve the noise immunity and reduce switching activity. Further, with the aid of a transistor in the stack, the sub-threshold current is reduced. Thus, the proposed domino is applicable for high-speed and low-power applications in deep sub-micro-range. Simulation results show that the proposed domino improves the noise immunity and figure of merit (FOM) by factors of 1.95 and 2.34, respectively, with respect to the conventional domino with a footer. Along with this improvement, 26% reduction is also observed in power consumption. The entire simulations for all the domino circuits are done at 45-nm CMOS technology by using SPECTRE simulator under the Cadence Virtuoso environment.

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