Timing analysis for extended burst-mode circuits

2002 ◽  
Author(s):  
S. Chakraborty ◽  
D.L. Dill ◽  
K.Y. Yun ◽  
Kun-Yung Chang
Keyword(s):  
Timing Analysis ◽  
Burst Mode

Design and Realization of SDRAM Controller Based on FPGA

2012 ◽  
Vol 241-244 ◽  
pp. 2233-2237
Author(s):  
Guo Hong Li ◽  
Zhen Wu
Keyword(s):  
Timing Analysis ◽  
Data Communication ◽  
Burst Mode ◽  
Full Page ◽  
Sdram Controller

This article introduces a SDRAM controller based on FPGA. It describes the architecture of controller and takes explain for each module .There is also a timing analysis about data communication between FPGA and SDRAM before post-simulation. Through board verification , a burst mode with auto precharge and full-page mode without auto precharge are achieved and the highest bandwidth in each mode are listed.

Effective ONU Accommodation through PON Systems with Multi-Stage Splitter Configuration Using ALC Burst-Mode SOAs

2014 ◽  
Vol E97.B (2) ◽  
pp. 432-440 ◽  
Author(s):  
Masamichi FUJIWARA ◽  
Ken-Ichi SUZUKI ◽  
Naoto YOSHIMOTO
Keyword(s):  
Burst Mode ◽  
Multi Stage

Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level

2010 ◽  
Vol 52 (4) ◽  
Author(s):  
Dominik Lorenz ◽  
Georg Georgakos ◽  
Ulf Schlichtmann
Keyword(s):  
Timing Analysis ◽  
Combinatorial Circuits

Timing analysis of worst case with direct NM of OSEK NM

2008 ◽  
Author(s):  
Chang-Wan Son ◽  
Jin-Ho Kim ◽  
Tae-Yoon Moon ◽  
Key-Ho Kwon ◽  
Sung-Ho Hwang ◽  
...  
Keyword(s):  
Timing Analysis ◽  
Worst Case
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